KVM support on XU4 running Ubuntu 18.04

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jwilson
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KVM support on XU4 running Ubuntu 18.04

Post by jwilson » Sat May 23, 2020 9:11 pm

Here are the steps I followed:

Flashed Ubuntu 18.04.3 LTS (v1.2) from https://wiki.odroid.com/odroid-xu4/os_i ... 10-minimal on to a clean eMMC. Booted the XU4, then compiled the kernel with KVM support as follows:

$ sudo -i
$ apt update
$ apt install git bc libssl-dev libncurses5-dev
$ git clone --depth 1 https://github.com/hardkernel/linux -b odroidxu4-4.14.y
$ cd linux
$ patch -p1 < /home/user/patchfile
$ make odroidxu4_kvm_defconfig
$ make -j 8
$ make modules
$ make modules_install
$ make zImage dtbs
$ cp arch/arm/boot/zImage /media/boot/zImage_kvm
$ cp arch/arm/boot/dts/exynos5422-odroidxu4-kvm.dtb /media/boot/

followed by an edit of /media/boot/boot.ini as follows:

# modify /media/boot/boot.ini
(......)
# Load kernel, initrd and dtb in that sequence
fatload mmc 0:1 0x40008000 zImage_kvm
(......)
if test "${board_name}" = "xu4"; then fatload mmc 0:1 0x44000000 exynos5422-odrooidxu4-kvm.dtb; setenv fdtloaded "true"; fi
(......)

After a reboot,

$ dmesg | grep HYP

[ 0.188912] CPU: All CPU(s) started in HYP mode.

$ dmesg | grep kvm

[ 0.794932] kvm [1]: 8-bit VMID
[ 0.796430] kvm [1]: vgic interrupt IRQ16
[ 0.796898] kvm [1]: Hyp mode initialized successfully

$ cat /proc/interrupts | grep arch_timer
58: 0 0 0 0 0 0 0 0 GICv2 29 Level arch_timer
59: 0 0 0 0 0 0 0 0 GICv2 30 Level arch_timer

$ kvm-ok
INFO: Your CPU does not support KVM extensions
KVM acceleration can NOT be used

Can anyone please point out what am I missing here? Why is the hardware KVM support not getting enabled?

Thanks.

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tony.hong
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Re: KVM support on XU4 running Ubuntu 18.04

Post by tony.hong » Tue May 26, 2020 12:01 pm

What are patchfiles?

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tony.hong
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Re: KVM support on XU4 running Ubuntu 18.04

Post by tony.hong » Tue May 26, 2020 12:48 pm

is this it?

Code: Select all

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index cae6bb4..43bb86a 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -75,7 +75,7 @@ ENDPROC(cpu_v7_btbinv_switch_mm)
  *	Cortex-A15 requires ACTLR[0] to be set from secure in order
  *	for the icache invalidation to also invalidate the BTB.
  */
-ENTRY(cpu_ca15_switch_mm)
+/*ENTRY(cpu_ca15_switch_mm)
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c7, c5, 0			@ ICIALLU
 	mmid	r2, r2
@@ -85,7 +85,7 @@ ENTRY(cpu_ca15_switch_mm)
 	isb
 #endif
 	ret	lr
-ENDPROC(cpu_ca15_switch_mm)
+ENDPROC(cpu_ca15_switch_mm) */
 
 #ifdef __ARMEB__
 #define rl r3

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