How does the DRAM communicate with Amlogic s905

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pommepoire
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How does the DRAM communicate with Amlogic s905

Unread post by pommepoire » Wed Jul 11, 2018 12:41 am

Hi.


According to the schematic of ODROID-C2 (https://dn.odroid.com/S905/Schematic/od ... 150930.pdf) and the Amlogic S905 datasheet (https://dn.odroid.com/S905/DataSheet/S9 ... V1.1.4.pdf) there are 32 pins dedicated to I/O with DRAM (DQ0 to DQ31) on the SoC.

But the schematics tell us that the ODROID-C2 uses DDR3 whom width is 8 bits and there are 2 chips in a rank and 2 ranks (2 ranks of 2 chips equals 4 chips in total).
For that I know about DRAM in a classical computer a rank gives 64 bits and the memory controllers are also 64 bits (in DDR3/DDR4 each transfer is a burst of 8 * 64 bits so 64 bytes which is the classical size of a cache line, moreover the Cortex A53 has 64 bytes width cache lines).

So how does it work with ODROID? Are the two ranks accessed together to give the 32 bits? And two transfer to get 64 bytes?
Or is there only one rank accessed and a cacheline is transfered in multiples transfer?


Thank you in advance and best regards.

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mad_ady
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Re: How does the DRAM communicate with Amlogic s905

Unread post by mad_ady » Wed Jul 11, 2018 12:56 am

As far as I know all chips are used at the same time (data is divided amongs the chips). If you remove one chip you lose data from all addresses.

pommepoire
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Re: How does the DRAM communicate with Amlogic s905

Unread post by pommepoire » Wed Jul 11, 2018 3:11 am

Thank you for your answer.

It also seems logical for me since the 32 pins of the S905 must be provided.
But in the datasheet of the S905 on pages 269-270 some bits of the registers are used to select a rank, so those bits are set to 0 to indicate to not select a rank?

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