How much is the bitbang clock speed of c4 using spi?

[jalhalgeyo]

I know the bitbang speed is max 100MHz for spi.
But actual speed is about 380kHz.
What should I handle something?

[tobetter]

What is your OS version now and what device is connected to your SPI port? Did you test the SPI with a device tree overlay or /dev/spi* node?

[mctom]

So I understand you have bit-banged SPI interface yourself using GPIO calls only, and it runs slower than expected?
How did you implement it? What GPIO libraries did you use and what language? A code sample would be appreciated.

EDIT: Or is it that you're using SPI to bitbang one GPIO at high speed? That's clever.
Still, showing some code may help us understand what's going on.

[odroid]

0.38Mhz is way too slow.
We could get near 72Mhz when we tested a SPI TFT LCD almost two years ago.
viewtopic.php?f=205&t=40655

[jalhalgeyo]

okay of course!! I can show you my code for bitbang.
In order to test the bit-bang speed, I changed to the from spi-pin to gpio-pin.
I chaged these pins. - gpiox_8, 9, 11, 10
I just used spi-gpio platform.
I used same driver code. I updated additional code in the dts.
Do you have any suggestion?
- driver codes

Code: Select all

void spi_trx(uint8_t *pTxBuff, uint8_t *pRxBuff, int nLen) {
 	struct spi_transfer t;
 	struct spi_message	m;

  	spi_bus_lock(gSPI->spi->master);

	memset(&t, 0, sizeof(t));
	t.tx_buf = pTxBuff;
	t.rx_buf = pRxBuff;
	t.len = nLen;
	t.bits_per_word = 8;		// spi master supports only 8bit mode
	t.delay_usecs = 2;
	if (qspi) {
		t.rx_nbits = SPI_NBITS_QUAD;
	}

  	spi_message_init(&m);
  	spi_message_add_tail(&t, &m);

  	ret = spi_sync_locked(gSPI->spi, &m);

	spi_bus_unlock(gSPI->spi->master);
}

meson64_odroidc4.dts
spi_gpio {
		status = "okay";
		compatible = "spi-gpio";
		#address-cells = <0x1>;
		ranges;

		gpio-sck = <&gpio GPIOX_11 0>;
		gpio-mosi = <&gpio GPIOX_8 0>;
		gpio-miso = <&gpio GPIOX_9 0>;
		cs-gpios = <&gpio GPIOX_10 0>;
		num-chipselects = <1>;

		/* clients */
		spidev@1 {
			compatible = "my-spi";
			spi-max-frequency = <100000000>;
			reg = <0>;
		};
	};

[jalhalgeyo]

We could get about 400Khz of bitbang SPI speed on the ODROID-C2 several years ago.
https://wiki.odroid.com/odroid-c2/appli ... _odroid-c2
Note that, we had to use the bitbang SPI because the SoC on the C2 board had no hardware SPI.
But the SoC on the C4 has a quite fast hardware SPI.

Since you are using a software bitbang gpio-SPI on your C4, the speed 380Khz is very normal.
Is there any specific reason not using the hardware SPI?

[jalhalgeyo]

What is your OS version now and what device is connected to your SPI port? Did you test the SPI with a device tree overlay or /dev/spi* node?

I described below.
The os version is ubuntu20.04 (4.9.337+).

[jalhalgeyo]

We could get about 400Khz of bitbang SPI speed on the ODROID-C2 several years ago.
https://wiki.odroid.com/odroid-c2/appli ... _odroid-c2
Note that, we had to use the bitbang SPI because the SoC on the C2 board had no hardware SPI.
But the SoC on the C4 has a quite fast hardware SPI.

Since you are using a software bitbang gpio-SPI on your C4, the speed 380Khz is very normal.
Is there any specific reason not using the hardware SPI?

The reason that I tried to use bit-bang spi is that I want to implement quad spi.
Because C4 doesn't have qspi option. So I tried to implement the qspi-bitbang.
You mean, if I use the bit-bang spi, it can't get the speed over 380Khz. right?

[odroid]

Right.
The maximum GPIO toggling speed could be about 2~3Mhz.
But if you add read-modify-write functions to implement the software SPI, the actual clock speed must lower than 1Mhz.

When we wrote our own driver to reduce the overhead in the generic bitbang SPI driver in Kernel, we could get slightly over 2Mhz with the customized parallel bitbang driver.
But it was an one-direction (output only) driver.
viewtopic.php?p=149028#p149028
If we needed Write and Read functions both, the speed could much lower as expected.

[jalhalgeyo]

Right.
The maximum GPIO toggling speed could be about 2~3Mhz.
But if you add read-modify-write functions to implement the software SPI, the actual clock speed must lower than 1Mhz.

When we wrote our own driver to reduce the overhead in the generic bitbang SPI driver in Kernel, we could get slightly over 2Mhz with the customized parallel bitbang driver.
But it was an one-direction (output only) driver.
viewtopic.php?p=149028#p149028
If we needed Write and Read functions both, the speed could much lower as expected.

I realized it is impossible. so I'll look for a chip that supports quad spi.
I appreciate your response.

[mctom]

Some FTDI chips support quad SPI and other interfaces, and will work with any Linux machine.
https://ftdichip.com/products/ft4222h/
This one claims some 53Mbps in Quad SPI mode.

[jalhalgeyo]

Some FTDI chips support quad SPI and other interfaces, and will work with any Linux machine.
https://ftdichip.com/products/ft4222h/
This one claims some 53Mbps in Quad SPI mode.

Yes. I already used ftdi chip for quad spi. But it didn't statisfy the clock speed I want.
Recently, I figured out the solution one of stm chips.
So I'll try to implement the quad spi.
Thanks for helping me.