boot loop after reboot with HC4

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dnr
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boot loop after reboot with HC4

Post by dnr »

I've set up my HC4 and it's working well, with one exception:

When I manually reboot it (e.g. the reboot command over ssh), it doesn't come back up. On the serial console I see that it's stuck in a loop:

Code: Select all

...
[  OK  ] Reached target Shutdown.
[  OK  ] Reached target Final Step.
[  OK  ] Finished Reboot.
[  OK  ] Reached target Reboot.
[  131.312622] watchdog: watchdog0: watchdog did not stop!
[  131.896454] reboot: Restarting system
bl31 reboot reason: 0xd
bl31 reboot reason: 0x0
system cmd  1.
SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;CHK:1F;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected_
L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180

TE: 152094

BL2 Built : 22:54:32, Apr 28 2020. g12a ga659aac-dirty - changqing.gao@droid11

Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Apr 28 2020 22:54:28
board id: 7
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 255
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==94 ps 8
R0_TxDqDly_Margi==118 ps 10


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001_

soc_vref_reg_value 0x 00000050 0000004e 0000004e 00000050 00000050 00000050 00000051 0000004f 0000004d 00000052 0000004e 0000004e 0000004f 0000004e 0000004f 0000004f 0000004e 0000004f 00000050 0000004e 0000004d 0000004e 00000050 0000004d 0000004e 0000004f 0000004f 0000004d 0000004f 0000004d 0000004f 0000004e dram_vref_reg_value 0x 00000022
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:43
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00700024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 407
result report
boot times 1Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x00098000, part: 0
sd/emmc cmd 18 arg 0x000003c1 status 01f2200f
sdio read data fail
reset...
SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;CHK:1F;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
... (repeats with increasing boot count number)
I've wiped the SPI flash so it's booting directly from the SD card. The SD card is a 64GB SanDisk Ultra UHS-1, this one: https://ameridroid.com/products/sandisk ... 6020050978

On the card is U-Boot 2021.01, although it looks like it's not getting that far.

If I remove the power and plug it in again, it boots properly.

Any ideas for how I can get reboot to work? I'd really like to be able to upgrade and reboot it unattended.

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Re: boot loop after reboot with HC4

Post by tobetter »

Which OS are you running on your SD card?
Since you have wiped the SPI flash memory and the version of U-Boot is 2021.01, I guess it would be Armbian? Then can you please share the problem with their forum as well?

Also can you try with Hardkernel's stock OS image with your SD card if it also makes the issue?
https://wiki.odroid.com/odroid-hc4/os_images/ubuntu

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Re: boot loop after reboot with HC4

Post by igorpec »

Armbian boot log:

Code: Select all

SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180

TE: 388354

BL2 Built : 20:29:41, Jun 18 2019. g12a ga659aac - luan.yuan@droid15-sz

Board ID = 4
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:37
board id: 4
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 255
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==106 ps 9
R0_TxDqDly_Margi==118 ps 10


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001

soc_vref_reg_value 0x 00000053 00000054 00000053 00000054 00000052 00000055 00000055 00000053 00000053 00000051 00000053 00000056 00000050 00000053 00000055 00000054 00000051 00000051 00000052 00000051 00000051 00000051 00000052 00000052 00000051 00000051 00000054 00000052 00000054 00000051 00000053 00000052 dram_vref_reg_value 0x 00000021
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:43
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00700024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 445
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x00098000, part: 0
bl2z: ptr: 05129330, size: 00001e40
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3386-3b31431 2019-05-21 10:41:54 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
2b 0c 10 00 01 13 21 00 00 01 34 39 32 47 38 50
[0.017354 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:57:33, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2021.04-armbian (May 06 2021 - 18:09:35 +0000) odroid-c4/hc4

Model: Hardkernel ODROID-C4
SoC:   Amlogic Meson SM1 (S905X3) Revision 2b:c (10:2)
DRAM:  3.8 GiB
MMC:   sd@ffe05000: 0, mmc@ffe07000: 1
In:    serial
Out:   serial
Err:   serial
Board variant: c4
Net:   eth0: ethernet@ff3f0000
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot/boot.scr
7155 bytes read in 6 ms (1.1 MiB/s)
## Executing script at 08000000
161 bytes read in 2 ms (78.1 KiB/s)
15985096 bytes read in 685 ms (22.3 MiB/s)
25453056 bytes read in 1129 ms (21.5 MiB/s)
72338 bytes read in 9 ms (7.7 MiB/s)
232 bytes read in 6 ms (37.1 KiB/s)
Applying kernel provided DT fixup script (meson-fixup.scr)
## Executing script at 32000000
## Loading init Ramdisk from Legacy Image at 13000000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (gzip compressed)
   Data Size:    15985032 Bytes = 15.2 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 04080000
   Booting using the fdt blob at 0x4080000
   Loading Ramdisk to 3f0c1000, end 3ffff988 ... OK
   Loading Device Tree to 000000003f046000, end 000000003f0c0fff ... OK

Starting kernel ...

[    4.400325] panfrost ffe40000.gpu: dev_pm_opp_set_regulators: no regulator (mali) found: -19

Armbian 21.08.0-trunk.77 Hirsute ttyAML0

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Re: boot loop after reboot with HC4

Post by dnr »

Thanks for the quick reply!

I'm using NixOS (21.05) with kernel 5.11.18 from your tree (commit a5b0f896fba4385d7b847bc92b4cb6b5d43e5a4d). I can share the specific config if it helps. I configured it by starting from the config in your Ubuntu 20.10 kernel 5.11 image (20210301) and making a few small changes required by NixOS, and disabling some big chunks of unnecessary hardware support (to build faster).

Do you think the problem is the OS leaving the SD card (or SD card peripheral) in a bad state?

Unfortunately I don't have a spare SD card here (at least not one of the same model), so I'd have to back it up somewhere before I can flash it with a stock image. I'm not sure I'll be able to do it any time soon.

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Re: boot loop after reboot with HC4

Post by tobetter »

dnr wrote:
Wed Jul 14, 2021 5:34 am
Thanks for the quick reply!

I'm using NixOS (21.05) with kernel 5.11.18 from your tree (commit a5b0f896fba4385d7b847bc92b4cb6b5d43e5a4d). I can share the specific config if it helps. I configured it by starting from the config in your Ubuntu 20.10 kernel 5.11 image (20210301) and making a few small changes required by NixOS, and disabling some big chunks of unnecessary hardware support (to build faster).

Do you think the problem is the OS leaving the SD card (or SD card peripheral) in a bad state?

Unfortunately I don't have a spare SD card here (at least not one of the same model), so I'd have to back it up somewhere before I can flash it with a stock image. I'm not sure I'll be able to do it any time soon.
Ok, I didn't notice NixOS. :)

My guess is that SD card is not compatible when rebooting only as you observed, I think using the Petitboot will prevent the issue. Having the Petitboot would delay boot, but you can set up the boot delay which is 10 by default in System Settings. I think it's worth to try, IMO.

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Re: boot loop after reboot with HC4

Post by dnr »

I tried for a long time and I couldn't get petitboot to boot a 5.x kernel :( It would hang somewhere before passing control to the kernel. I tried all sorts of stuff in boot.ini, different load addresses, different dtbs, command lines, and nothing worked. It was very frustrating because there's no documentation on how exactly petitboot was interpreting boot.ini (differently from u-boot). Once I switched to using u-boot on the sd card, I was able to use the interactive shell to try a few options and easily made a boot.scr generator for NixOS, which has been working great.

I appreciate the idea behind petitboot on flash, but it really just didn't work at all for my use-case (headless, unattended, OS on sd card).

I don't mind the boot delay, but I'm not sure I want to try experimenting with petitboot again without a guarantee that I can even get it working (with a 5.x kernel and NixOS).

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Re: boot loop after reboot with HC4

Post by tobetter »

dnr wrote:
Wed Jul 14, 2021 6:07 am
I tried for a long time and I couldn't get petitboot to boot a 5.x kernel :( It would hang somewhere before passing control to the kernel. I tried all sorts of stuff in boot.ini, different load addresses, different dtbs, command lines, and nothing worked. It was very frustrating because there's no documentation on how exactly petitboot was interpreting boot.ini (differently from u-boot). Once I switched to using u-boot on the sd card, I was able to use the interactive shell to try a few options and easily made a boot.scr generator for NixOS, which has been working great.

I appreciate the idea behind petitboot on flash, but it really just didn't work at all for my use-case (headless, unattended, OS on sd card).

I don't mind the boot delay, but I'm not sure I want to try experimenting with petitboot again without a guarantee that I can even get it working (with a 5.x kernel and NixOS).
My 5.x kernel can boot with the Petitboot and it does not require a complicated or special commands. I would be happy to help you if you share the kernel image, ramdisk and your boot script. Then I can test to boot with your kernel on HC4 with the Petitboot. We can work together to boot NixOS.

One issue you have now is that you need another SD card to restore the Petitboot.
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Re: boot loop after reboot with HC4

Post by dnr »

Thanks so much for the offer (and your work on getting current kernels to run on it)!

I won't be able to really try this for several months, because I have to leave the HC4 somewhere where I don't have easy access to it. (For now I can ask someone to unplug it when it needs to be rebooted.)

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Re: boot loop after reboot with HC4

Post by tobetter »

dnr wrote:
Wed Jul 14, 2021 6:36 am
Thanks so much for the offer (and your work on getting current kernels to run on it)!

I won't be able to really try this for several months, because I have to leave the HC4 somewhere where I don't have easy access to it. (For now I can ask someone to unplug it when it needs to be rebooted.)
Ok, please do not hesitate to reach me whenever you have a chance to manage your HC4 and want to try to fix the rebooting issue. I will gratefully try to help you. Who knows if NixOS is ported or rebooting issus is fixed. :)

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Re: boot loop after reboot with HC4

Post by igorpec »

tobetter wrote:
Wed Jul 14, 2021 10:34 am
and want to try to fix the rebooting issue. I will gratefully try to help you. Who knows if NixOS is ported or rebooting issus is fixed. :)
Rebooting on HC4 / Odroid N2 with mainline derived kernel is still hit and miss, not rock stable. Current dirty hacks that are added to Hardkernel code are breaking some other boards to boot successfully and vice versa - which is not a good idea when using common mainline kernel. Which is the case for general distributions that only knows/has one kernel.

It has to be done differently.

We are trying to fix this problem for our users, general public and other vendors at the same time. Mainline kernel has to support both, but ofc proper solution is usually more time consuming. Here https://github.com/armbian/build/pull/2943 one can read our findings, current solution and ideas on better boot implementation for Odroids / other similar boards.
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Re: boot loop after reboot with HC4

Post by igorpec »

dnr wrote:
Wed Jul 14, 2021 6:36 am
on getting current kernels to run on it
Hardkernel support is certainly solid, most of other vendors are worse in this regard, but to be fair - most thanks regarding current kernel implementation on Amlogic SoC goes to https://linux-meson.com/doku.php - BayLibre and projects such as Libreelec, Armbian, ... which has tested and implemented things years before. Vendors needs much bigger overall usability, while for CLI only and special cases, things were good before. Even today, they are releasing mainline based images under their engineers names which goes with a lower responsibility and less costs.
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Re: boot loop after reboot with HC4

Post by tobetter »

igorpec wrote:
Wed Jul 14, 2021 5:12 pm
dnr wrote:
Wed Jul 14, 2021 6:36 am
on getting current kernels to run on it
Hardkernel support is certainly solid, most of other vendors are worse in this regard, but to be fair - most thanks regarding current kernel implementation on Amlogic SoC goes to https://linux-meson.com/doku.php - BayLibre and projects such as Libreelec, Armbian, ... which has tested and implemented things years before. Vendors needs much bigger overall usability, while for CLI only and special cases, things were good before. Even today, they are releasing mainline based images under their engineers names which goes with a lower responsibility and less costs.
So what's your point here?

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Re: boot loop after reboot with HC4

Post by igorpec »

tobetter wrote:
Wed Jul 14, 2021 7:51 pm
So what's your point here?
Extending perception? Sharing information, adding missed out information? The same as with technical problem our clients (and many others) have with your hardware - reboot instability - and where we already wasted substantiation amount of our time which is never compensated.

I know you already tried to provide proper solution. Just sharing where we get, what we know and which options we have to patch the problem. They came from a different perspective.
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Re: boot loop after reboot with HC4

Post by tobetter »

igorpec wrote:
Wed Jul 14, 2021 9:33 pm
tobetter wrote:
Wed Jul 14, 2021 7:51 pm
So what's your point here?
Extending perception? Sharing information, adding missed out information? The same as with technical problem our clients (and many others) have with your hardware - reboot instability - and where we already wasted substantiation amount of our time which is never compensated.
Sharing information? I believe you are not meaning the "Sharing" is one way information deliverry from a vendor to Armbian.
We have different users and clients who are trying to reach one who can help their problems. The problem might be a hardware or buggy software, the problem could be happened in a software but different software would be not. If the problem is from hardware, absolutely it should be discussed with a vendor, Hardkernel, at least I don't believe anyone me or someone else ask Armbian users to get help from Armbian for no reason. I don't complain about Armbian OS, since I can't judge, since I don't use it, since I don't look into it. But I respect Armbian OS itself, the effort your team made and its history. I think I can count the numbers how many times I have discussed with Armbian members for issues. Why do you want me to understand the effort you wasted for an issue what you have not tried to discuss with me? What compensation do you want me to understand for your effort?
I know you already tried to provide proper solution. Just sharing where we get, what we know and which options we have to patch the problem. They came from a different perspective.
Different perspective, we have different pespective. We are manaing a different software stack and solution might be same or different, a patch can be applied or not. I believe whatever the patch is, the resposiblity is taken by one who apply it. I also realized that a couple of patches from my Linux git branch are merged into Armbian tree, I have not shared them, have not been discussed, have not been questioned, have not acknolodged they are merged. I have no idea what issue you are working for, this does make me not to help you for the different software stack which may not have an issue. Do you want me to report you whatever I have and whatever it happens for an issue? Don't you think we need to respect each other before discussing about the effort?

I am from Hardkernel but I am not Hardkernel. Whatever noted here is my personal opinion as a Hardkernel staff and an ODROID lover.
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Re: boot loop after reboot with HC4

Post by igorpec »

tobetter wrote:
Thu Jul 15, 2021 12:09 am
I don't complain about Armbian OS
Whoever will not use your boot sw will run into problems. They started here
https://git.kernel.org/pub/scm/linux/ke ... 4dbec91791

and I am not sure that next commit fixes them - can't test this now. Its reproduced easily - if patch is reverted, VIM3 is failing a lot, if patch is in, Odroid hangs virtually at every reboot ... its probably not the only problem of such nature.
tobetter wrote:
Thu Jul 15, 2021 12:09 am
We are manaing a different software stack and solution might be same or different
In mainline future it is / should be only be one stack. Yes, we do have patches here, patches there, but we try to keep them under control. I am sure they are not problematic in mentioned troubles.
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