Change pin state and value with u-boot.

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aress
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Change pin state and value with u-boot.

Post by aress »

Hi.

I try to change pin mode and value at boot time with u-boot but i can't do that. This is what I do step by step;

1-) I run "make odroidn2_defconfig" command in u-boot directory in terminal.

Code: Select all

~/u-boot$ make odroidn2_defconfig
  GEN     ./Makefile
#
# configuration written to .config
#
2-) I add "gpio_direction_output()" function in /home/xx/u-boot/board/hardkernel/odroidn2/odroidn2.c file

Code: Select all

int board_init(void)
{
	board_led_alive(1);
	
#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
	board_usb_pll_disable(&g_usb_config_GXL_skt);
	board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
#endif /*CONFIG_USB_XHCI_AMLOGIC*/

	gpio_direction_output(477, 1);		/*My code is here*/

	return 0;
}
3-) I run "make" command in u-boot directory in terminal.

Code: Select all

~/u-boot$ make
  GEN     ./Makefile
scripts/kconfig/conf --silentoldconfig Kconfig
  CHK     include/config.h
  GEN     include/autoconf.mk
  GEN     include/autoconf.mk.dep
  CHK     include/config/uboot.release
  Using .. as source for U-Boot
  GEN     ./Makefile
  CHK     include/generated/version_autogenerated.h
  CHK     include/generated/timestamp_autogenerated.h
  UPD     include/generated/timestamp_autogenerated.h
  HOSTCC  tools/mkenvimage.o
  HOSTLD  tools/mkenvimage
  HOSTCC  tools/image-host.o
  HOSTCC  tools/dumpimage.o
  HOSTLD  tools/dumpimage
  HOSTCC  tools/mkimage.o
  HOSTLD  tools/mkimage
  AS      arch/arm/cpu/armv8/exceptions.o
  AS      arch/arm/cpu/armv8/cache.o
  AS      arch/arm/cpu/armv8/tlb.o
  AS      arch/arm/cpu/armv8/transition.o
  AS      arch/arm/cpu/armv8/a32_kernel_pre_entry.o
  LD      arch/arm/cpu/armv8/built-in.o
  AS      arch/arm/cpu/armv8/start.o
  CC      board/hardkernel/odroidn2/odroidn2.o
  LD      board/hardkernel/odroidn2/built-in.o
  CC      common/main.o
  CC      common/board_f.o
  CC      common/cmd_version.o
  LD      common/built-in.o
  CC      drivers/usb/gadget/f_fastboot.o
  LD      drivers/usb/gadget/built-in.o
  CC      lib/display_options.o
  LD      lib/built-in.o
  LD      u-boot
  OBJCOPY u-boot.srec
  OBJCOPY u-boot.bin
  OBJCOPY u-boot.hex
Building board/hardkernel/odroidn2/acs.bin
  CC      acs.c
  AS      acs_entry.S
  PP      acs.ld.S
  LD      /home/xx/u-boot/build/board/hardkernel/odroidn2/firmware/acs.elf
  OD      /home/xx/u-boot/build/board/hardkernel/odroidn2/firmware/acs.dump
  BIN     /home/xx/u-boot/build/board/hardkernel/odroidn2/firmware/acs.bin

Built /home/xx/u-boot/build/board/hardkernel/odroidn2/firmware/acs.bin successfully


	CPP task_entry.s
	CPP user_task.lds
	CC task_entry.o
	CC user_task.o
	CPP misc.s
	CC misc.o
	CC uart.o
	CC suspend.o
	CC lib/string.o
	CC lib/delay.o
	LD /home/xx/u-boot/build/scp_task/bl301.out
	OBJDUMP /home/xx/u-boot/build/scp_task/bl301.dis
	OBJCOPY /home/xx/u-boot/build/scp_task/bl301.bin
Building /home/xx/u-boot/build/fip/fip.bin...
Amlogic img found, use new FIP structure!
Updating "/home/xx/u-boot/build/fip/fip.bin"
Firmware Image Package ToC:
---------------------------
- SCP Firmware BL3-0: offset=0x4000, size=0xD400
- EL3 Runtime Firmware BL3-1: offset=0x14000, size=0x29328
- Non-Trusted Firmware BL3-3: offset=0x40000, size=0xAE220
---------------------------
# build final bootloader
Building /home/xx/u-boot/sd_fuse/u-boot.bin...
/home/xx/u-boot/sd_fuse/u-boot.bin is updated.
4-) jump to sd_fuse folder.

Code: Select all

~/u-boot$ cd sd_fuse
5-) I plug sdCard-Reader to Pc.

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/media/xx$ ls
BOOT   BOOT2  BOOT4  BOOT6  BOOT8   rootfs1  rootfs3
BOOT1  BOOT3  BOOT5  BOOT7  rootfs  rootfs2  rootfs4
rootfs4 and BOOT8 is my sdcard.

Code: Select all

/media/xx/BOOT8$ ls
 amlogic        config.ini       edid.bin                     uInitrd
 boot.ini       config.ini.old   Image.gz
 boot.ini.old   display.bin     'System Volume Information'
/media/xx/rootfs4$ ls
bin   dev  home  lost+found  mnt  proc        root  sbin  srv  tmp  var
boot  etc  lib   media       opt  resize.log  run   snap  sys  usr
6-) Finally I run the "sd_fusing.sh" command to upload the image to the sd card.

Code: Select all

~/u-boot/sd_fuse$ ./sd_fusing.sh /media/xx/BOOT8
[sudo] password for xx: 
dd: failed to open '/media/xx/BOOT8': Is a directory
Finished.
~/u-boot/sd_fuse$ ./sd_fusing.sh /media/xx/BOOT8
1669+1 records in
1669+1 records out
854896 bytes (855 kB, 835 KiB) copied, 0,0457094 s, 18,7 MB/s
eject: tried to use `/media/xx/BOOT8' as device name but it is no block device
eject: unable to find or open device for: `/media/xx/BOOT8'
Finished.
Am i forget something or do this completely wrong?

Thanks!

My System:
Type: ODROID-N2/N2Plus, Revision: 01, Memory: 4096MB Chip-Vendor: AMLogic
wiringPiVersion 3.7 Kernel version 4.9.236-97

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Re: Change pin state and value with u-boot.

Post by tobetter »

You should use the device node instead of the directory "/media/xx/BOOT". For example, if your SD card reader must be like " /dev/sdc" or "/dev/sdd"... depends on your host system. Another form is to use " /dev/disk/by-id/usb-YOUR-CARD-READER". If you are not sure which device to use, please share the output of the command "ls /dev/disk/by-id/*" .

aress
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Re: Change pin state and value with u-boot.

Post by aress »

Code: Select all

ls /dev/disk/by-id/*
/dev/disk/by-id/ata-VBOX_CD-ROM_VB2-01700376
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part1
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part2
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part5
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0-part1
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0-part2

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Thu Oct 22, 2020 9:43 pm

Code: Select all

ls /dev/disk/by-id/*
/dev/disk/by-id/ata-VBOX_CD-ROM_VB2-01700376
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part1
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part2
/dev/disk/by-id/ata-VBOX_HARDDISK_VBe5127d19-51c6b60f-part5
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0-part1
/dev/disk/by-id/usb-Generic_Mass-Storage-0:0-part2
I would try this command if one USB storage or card reader is attached.

sudo ./sd_fusing.sh /dev/disk/by-id/usb-Generic_Mass-Storage-0:0

aress
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Re: Change pin state and value with u-boot.

Post by aress »

Code: Select all

udo ./sd_fusing.sh /dev/disk/by-id/usb-Generic_Mass-Storage-0:0
[sudo] password for xx: 
1669+1 records in
1669+1 records out
854896 bytes (855 kB, 835 KiB) copied, 2,95705 s, 289 kB/s
Finished.
Thanks. it worked. but the system is not loaded. power and system leds are constantly on and screen is black.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Thu Oct 22, 2020 10:05 pm

Code: Select all

udo ./sd_fusing.sh /dev/disk/by-id/usb-Generic_Mass-Storage-0:0
[sudo] password for xx: 
1669+1 records in
1669+1 records out
854896 bytes (855 kB, 835 KiB) copied, 2,95705 s, 289 kB/s
Finished.
Thanks. it worked. but the system is not loaded. power and system leds are constantly on and screen is black.
If the blue LED is constantly on, this means your board stops at U-boot and probably it fails to load and run Linux kernel. I suspect that your memory card defects since you've flash U-boot to the first partition "/media/xx/BOOT" before.

Please check the U-boot log through UART.

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Re: Change pin state and value with u-boot.

Post by aress »

I installed clean system and installed u-boot as you said. now here is my odroid's log;

Code: Select all

 ÿ ô G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.†!,KúÍÑ…•}¥¹¥Ñ0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected 
L0:00000000
L1:00000703
L2:0000c067
L3:14000020
B2:00402000
B1:e0f83180

TE: 312178

BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13

Board ID = 5
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00050ba6
DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09
board id: 5
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 255
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==94 ps 8
R0_TxDqDly_Margi==106 ps 9


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00600024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass
 pre test  bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420
 aft test  bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420
non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 420
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0003c200, des: 0x0172c000, size: 0x00094c00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0

E30HDR

MVN_1=0x00000000

MVN_2=0x00000000

[Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz]

OPS=0x40

ring efuse init

chipver efuse init

29 0c 40 00 01 0e 10 00 00 02 39 31 4e 31 53 50 

[0.019858 Inits done]

secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):ab8811b
NOTICE:  BL31: Built : 15:03:31, Feb 12 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2015.01-dirty (Oct 22 2020 - 22:53:18)

DRAM:  3.5 GiB
Relocation Offset is: d6ef3000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7f84ac0
MMC:   aml_priv->desc_buf = 0x00000000d3ee3bc0
aml_priv->desc_buf = 0x00000000d3ee5f00
SDIO Port C: 0, SDIO Port B: 1
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x12000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
In:    serial
Out:   serial
Err:   serial
vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
vpu: driver version: v20190313
vpu: detect chip type: 9
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level = 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
cvbs_config_hdmipll_g12a
cvbs_set_vid2_clk
reading boot-logo.bmp.gz
** Unable to read file boot-logo.bmp.gz **
reading boot-logo.bmp
** Unable to read file boot-logo.bmp **
movi: not registered partition name, logo
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]set initrd_high: 0x3d800000
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3d800000 width=5760, height=2160
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 1.4 or below  div=10
Net:   dwmac.ff3f0000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01000
reading logo.bmp.gz
** Unable to read file logo.bmp.gz **
reading logo.bmp
** Unable to read file logo.bmp **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 1.4 or below  div=10
Hit Enter or space or Ctrl+C key to stop autoboot -- :  1  0 
reading boot.ini
2588 bytes read in 4 ms (631.8 KiB/s)
## Executing script at 01000000
reading config.ini
3491 bytes read in 4 ms (851.6 KiB/s)
ini: Imported display_autodetect as true
ini: Imported hdmimode as 1080p60hz
ini: Imported monitor_onoff as false
ini: Imported overscan as 100
ini: Imported sdrmode as auto
ini: Imported voutmode as hdmi
ini: Imported disablehpd as false
ini: Imported cec as true
ini: Imported disable_vu7 as true
ini: Imported maxcpus as 6
ini: Imported overlay_resize as 16384
ini: Imported overlay_profile as 
ini: Imported overlays as disable_spdif
HDMI cable is NOT connected
reading Image.gz
9324923 bytes read in 509 ms (17.5 MiB/s)
reading uInitrd
17663231 bytes read in 987 ms (17.1 MiB/s)
reading amlogic/meson64_odroid.dtb
** Unable to read file amlogic/meson64_odroid.dtb **
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
reading amlogic/overlays/odroidn2/disable_spdif.dtbo
360 bytes read in 7 ms (49.8 KiB/s)
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
Uncompressed size: 25031168 = 0x17DF200
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
## Loading init Ramdisk from Legacy Image at 03700000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
   Data Size:    17663167 Bytes = 16.8 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
load dtb from 0x1000000 ......
ERROR: Did not find a cmdline Flattened Device Tree
load dtb from 0x0 ......
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
## Executing script at 01000000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
HDMI cable is NOT connected
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
Error: Bad gzipped data
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
Unknown command '' - try 'help'
reading boot.scr
** Unable to read file boot.scr **
## Executing script at 03000000
Wrong image format for "source" command
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
## Executing script at 03000000
Wrong image format for "source" command
co-phase 0x2, tx-dly 0, clock 40000000
co-phase 0x2, tx-dly 0, clock 40000000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x12000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
switch to partitions #0, OK
mmc1 is current device
movi: not registered partition name, boot
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

movi: not registered partition name, dtbs
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
ee_gate_off ...
Wrong Image Format for bootm command
ERROR: can't get kernel image!
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
ee_gate_on ...
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
movi: not registered partition name, boot
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

movi: not registered partition name, dtbs
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
ee_gate_off ...
Wrong Image Format for bootm command
ERROR: can't get kernel image!
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
ee_gate_on ...
odroidn2#
Last edited by aress on Fri Oct 23, 2020 5:15 am, edited 1 time in total.

User avatar
tobetter
Posts: 6622
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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 5:04 am
odroid's log;

Code: Select all

 ÿ ô G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.†!,KúÍÑ…•}¥¹¥Ñ0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected 
L0:00000000
L1:00000703
L2:0000c067
L3:14000020
B2:00402000
B1:e0f83180

TE: 312178

BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13

Board ID = 5
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00050ba6
DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09
board id: 5
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 255
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==94 ps 8
R0_TxDqDly_Margi==106 ps 9


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00600024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass
 pre test  bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420
 aft test  bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420
non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 420
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0003c200, des: 0x0172c000, size: 0x00094c00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0

E30HDR

MVN_1=0x00000000

MVN_2=0x00000000

[Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz]

OPS=0x40

ring efuse init

chipver efuse init

29 0c 40 00 01 0e 10 00 00 02 39 31 4e 31 53 50 

[0.019858 Inits done]

secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):ab8811b
NOTICE:  BL31: Built : 15:03:31, Feb 12 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2015.01-dirty (Oct 22 2020 - 22:53:18)

DRAM:  3.5 GiB
Relocation Offset is: d6ef3000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7f84ac0
MMC:   aml_priv->desc_buf = 0x00000000d3ee3bc0
aml_priv->desc_buf = 0x00000000d3ee5f00
SDIO Port C: 0, SDIO Port B: 1
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x12000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
In:    serial
Out:   serial
Err:   serial
vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
vpu: driver version: v20190313
vpu: detect chip type: 9
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level = 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
cvbs_config_hdmipll_g12a
cvbs_set_vid2_clk
reading boot-logo.bmp.gz
** Unable to read file boot-logo.bmp.gz **
reading boot-logo.bmp
** Unable to read file boot-logo.bmp **
movi: not registered partition name, logo
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]set initrd_high: 0x3d800000
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3d800000 width=5760, height=2160
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 1.4 or below  div=10
Net:   dwmac.ff3f0000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01000
reading logo.bmp.gz
** Unable to read file logo.bmp.gz **
reading logo.bmp
** Unable to read file logo.bmp **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 1.4 or below  div=10
Hit Enter or space or Ctrl+C key to stop autoboot -- :  1  0 
reading boot.ini
2588 bytes read in 4 ms (631.8 KiB/s)
## Executing script at 01000000
reading config.ini
3491 bytes read in 4 ms (851.6 KiB/s)
ini: Imported display_autodetect as true
ini: Imported hdmimode as 1080p60hz
ini: Imported monitor_onoff as false
ini: Imported overscan as 100
ini: Imported sdrmode as auto
ini: Imported voutmode as hdmi
ini: Imported disablehpd as false
ini: Imported cec as true
ini: Imported disable_vu7 as true
ini: Imported maxcpus as 6
ini: Imported overlay_resize as 16384
ini: Imported overlay_profile as 
ini: Imported overlays as disable_spdif
HDMI cable is NOT connected
reading Image.gz
9324923 bytes read in 509 ms (17.5 MiB/s)
reading uInitrd
17663231 bytes read in 987 ms (17.1 MiB/s)
reading amlogic/meson64_odroid.dtb
** Unable to read file amlogic/meson64_odroid.dtb **
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
reading amlogic/overlays/odroidn2/disable_spdif.dtbo
360 bytes read in 7 ms (49.8 KiB/s)
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
Uncompressed size: 25031168 = 0x17DF200
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
## Loading init Ramdisk from Legacy Image at 03700000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
   Data Size:    17663167 Bytes = 16.8 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
load dtb from 0x1000000 ......
ERROR: Did not find a cmdline Flattened Device Tree
load dtb from 0x0 ......
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
## Executing script at 01000000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
HDMI cable is NOT connected
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
Error: Bad gzipped data
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
Unknown command '' - try 'help'
reading boot.scr
** Unable to read file boot.scr **
## Executing script at 03000000
Wrong image format for "source" command
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
## Executing script at 03000000
Wrong image format for "source" command
co-phase 0x2, tx-dly 0, clock 40000000
co-phase 0x2, tx-dly 0, clock 40000000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x12000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
switch to partitions #0, OK
mmc1 is current device
movi: not registered partition name, boot
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

movi: not registered partition name, dtbs
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
ee_gate_off ...
Wrong Image Format for bootm command
ERROR: can't get kernel image!
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
ee_gate_on ...
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
movi: not registered partition name, boot
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

movi: not registered partition name, dtbs
movi - Read/write command from/to SD/MMC for ODROID board

Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
    - <read|write>  the command to access the storage
    - <offset>  the offset from the start of given partiton in lba
    - <address>  the memory address to load/store from/to the storage device
    - [<length>]  the size of the block to read/write in bytes
    - all parameters must be hexa-decimal only

[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
Bad Linux ARM64 Image magic!
ee_gate_off ...
Wrong Image Format for bootm command
ERROR: can't get kernel image!
[rsvmem] get fdtaddr NULL!
rsvmem - reserve memory

Usage:
rsvmem check                   - check reserved memory
rsvmem dump                    - dump reserved memory

rsvmem check failed
ee_gate_on ...
odroidn2#
This error convince me that your U-boot build is failed or not working properly for some reason, this error shows that your U-boot does not load the decent device tree file which is like meson64_odroidn2.dtb or meson64_odroidn2_plus.dtb.

Code: Select all

reading amlogic/meson64_odroid.dtb
** Unable to read file amlogic/meson64_odroid.dtb **
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
Did you change any other code than GPIO setting?

aress
Posts: 19
Joined: Tue Oct 20, 2020 11:12 pm
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Re: Change pin state and value with u-boot.

Post by aress »

I didn't change anything in the code except "gpio_direction_output(477, 1);". But I changed /media/boot/config.ini file like that -> viewtopic.php?t=40557.

User avatar
tobetter
Posts: 6622
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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 5:27 am
I didn't change anything in the code except "gpio_direction_output(477, 1);". But I changed /media/boot/config.ini file like that -> viewtopic.php?t=40557.
Then check if your boot.ini contains the line with meson64_odroid${variant}.dtb and replace it with meson64_odroidn2_plus.dtb. Also from the U-boot command line, please do run this command - print $variant - and share with me the output.

By the way, what command did you use to download the U-boot source tree?

aress
Posts: 19
Joined: Tue Oct 20, 2020 11:12 pm
languages_spoken: english
ODROIDs: n2/n2+
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Re: Change pin state and value with u-boot.

Post by aress »

I use "git clone https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01" command from https://wiki.odroid.com/odroid-n2/softw ... ing_u-boot.

boot.ini file contains "meson64_odroid${variant}.dtb" and i changed with "meson64_odroidn2_plus.dtb".

then odroid works

but when i try to access with vnc, there is black screen.

i just access with putty.

and i don't know how to use U-boot command line. I will write the result of "print $variant" when I find out how to do it.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 3:58 pm
I use "git clone https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01" command from https://wiki.odroid.com/odroid-n2/softw ... ing_u-boot.

boot.ini file contains "meson64_odroid${variant}.dtb" and i changed with "meson64_odroidn2_plus.dtb".

then odroid works

but when i try to access with vnc, there is black screen.

i just access with putty.

and i don't know how to use U-boot command line. I will write the result of "print $variant" when I find out how to do it.
Ok, here is a small problem.
Please use the branch odroidg12-v2015.01 instead of odroidn2-v2015.01.
Sorry for the confusion, Wiki a bit out-dated and now it's fixed.

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Re: Change pin state and value with u-boot.

Post by aress »

Thanks. i changed repo like u said and everythings looks fine except gpio 477 didn't change.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 8:31 pm
Thanks. i changed repo like u said and everythings looks fine except gpio 477 didn't change.
What's the problem with GPIO 477?

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Re: Change pin state and value with u-boot.

Post by aress »

I want to change the 19-21-23-24 pin of the 40 pin header to low output at boot time. but for now I'm trying to change any pin to learn.
when i run "gpio readall" command, this pin is not changed.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 9:13 pm
I want to change the 19-21-23-24 pin of the 40 pin header to low output at boot time. but for now I'm trying to change any pin to learn.
when i run "gpio readall" command, this pin is not changed.
So haven't you success to set low to any pin?
The command gpio readall is executed in Linux, not U-boot...right?

Can you share what's the purpose of setting low such pins?

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Re: Change pin state and value with u-boot.

Post by aress »

No. i haven't success to set low to any pin.
"gpio readall" was run on ubuntu:
Image
there are modules on the other end of the pins. modules work when pins are high.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Fri Oct 23, 2020 10:09 pm
No. i haven't success to set low to any pin.
"gpio readall" was run on ubuntu:
Image
there are modules on the other end of the pins. modules work when pins are high.
If you want to make a pin high when Linux is running, you should set the GPIO on Linux kernel, not U-boot.

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Re: Change pin state and value with u-boot.

Post by aress »

tobetter wrote:
Fri Oct 23, 2020 11:36 pm
aress wrote:
Fri Oct 23, 2020 10:09 pm
No. i haven't success to set low to any pin.
"gpio readall" was run on ubuntu:
Image
there are modules on the other end of the pins. modules work when pins are high.
If you want to make a pin high when Linux is running, you should set the GPIO on Linux kernel, not U-boot.
i can change any pin from terminal or on linux.
but i read out pins with multimeter when odroid booting and after that.
and pins level are high(3.3V) although pins are input.
i want the pins to be output low up to i change it. even at boot time.

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Re: Change pin state and value with u-boot.

Post by aress »

In this post -> viewtopic.php?t=29587 odroid said:
odroid wrote:
Wed Jan 17, 2018 6:17 pm
Refer this link to check the initial level of the Shifter Shield GPIOs.
https://wiki.odroid.com/odroid-xu4/hard ... eld_40_pin
Since most of them are input, adding a pull-down resistor will meet your requirement probably.

You need to change the DeviceTree and other GPIO settings in bootloader and kernel GPIO drivers if you really want to change the default mode/level.
Which pins do you want to change to output-low?
Why do you need output-low pins?
and a few post later, odroid said again:
odroid wrote:
Thu Jan 18, 2018 7:08 pm
GPIO #25 (Pin #26) should be input(hi-Z) as you saw.
So you can change it to output-low with your software.
If you need a low-level on input pin, you have to add a pull-down resistor.
But the pull-down resistor must be 50Kohm or higher as described in the WiKi page.
https://wiki.odroid.com/accessory/add-o ... ift_shield

If you really want to change the bootloader, you have to learn how to build the u-boot first,
https://wiki.odroid.com/odroid-xu4/soft ... t_mainline
So I thought this can be done with u-boot. m i wrong?

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Re: Change pin state and value with u-boot.

Post by odroid »

@aress,
You are on the right track.
@tobetter will help you when he has a time slot.

Meanwhile, check the GPIO pin state on the u-boot stage with a USB-UART serial console cable.
You also need to disable the SPI boot to avoid any side effects.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Sat Oct 24, 2020 2:04 am
tobetter wrote:
Fri Oct 23, 2020 11:36 pm
aress wrote:
Fri Oct 23, 2020 10:09 pm
No. i haven't success to set low to any pin.
"gpio readall" was run on ubuntu:
Image
there are modules on the other end of the pins. modules work when pins are high.
If you want to make a pin high when Linux is running, you should set the GPIO on Linux kernel, not U-boot.
i can change any pin from terminal or on linux.
but i read out pins with multimeter when odroid booting and after that.
and pins level are high(3.3V) although pins are input.
i want the pins to be output low up to i change it. even at boot time.
What/how did you run or change to set low any GPIO on Linux? What I am also curious if you are going to switch the pin state.

Also keep in mind that, you have to touch two places U-boot and Kernel, you need to do one after another.

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Re: Change pin state and value with u-boot.

Post by aress »

i couldn't find anything useful about changing gpio state for odroid at startup.
i just found i have to change device tree and config.ini. but What should I change in the kernel?
Does changing kernel mean changing devicetree?
what are the steps of this whole process?
Can you give me an example or an explanation link to help me understand this?

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Tue Oct 27, 2020 11:32 pm
i couldn't find anything useful about changing gpio state for odroid at startup.
i just found i have to change device tree and config.ini. but What should I change in the kernel?
Does changing kernel mean changing devicetree?
what are the steps of this whole process?
Can you give me an example or an explanation link to help me understand this?
You will need to change the device tree for kernel part.
Are you going to change the GPIO status after kernel boot? If so are you going to use an app or will you use a script?

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Re: Change pin state and value with u-boot.

Post by aress »

I decompiled device tree files and try to understand the contents of the file. But i didn't see any gpio process in files. There are just spi, i2c, spdif, usb, uart etc. in files.
tobetter wrote:
Tue Oct 27, 2020 11:39 pm
You will need to change the device tree for kernel part.
Are you going to change the GPIO status after kernel boot? If so are you going to use an app or will you use a script?
Yes. I am going to change the GPIO status after kernel boot with an app that uses WiringPi.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Mon Nov 02, 2020 9:42 pm
I decompiled device tree files and try to understand the contents of the file. But i didn't see any gpio process in files. There are just spi, i2c, spdif, usb, uart etc. in files.
tobetter wrote:
Tue Oct 27, 2020 11:39 pm
You will need to change the device tree for kernel part.
Are you going to change the GPIO status after kernel boot? If so are you going to use an app or will you use a script?
Yes. I am going to change the GPIO status after kernel boot with an app that uses WiringPi.
If you are going to use WiringPi, you should not change the device tree since WringPi does use the 'gpio' framework. The device tree is for a device drivers in the kernel space. I believe you are able to use WiringPi to change the pin state and most/all pins would be able to work as expected.

If you concern is the default status of GPIO before running WiringPi, you must change the default state in U-boot. This is what you've tried at first if I remember correctly. What I am not sure as of now is if the GPIO pins set in U-boot keeps its state while Linux kernel loads and runs until your WiringPi based app starts. If you want to know more specific method, you can pick up one or two pins and we both can try to set.

One question, do you want to use WiringPi only to control GPIO or are you going to handle other pins like i2c or spi?

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Re: Change pin state and value with u-boot.

Post by aress »

tobetter wrote:
Tue Nov 03, 2020 8:16 pm
If you are going to use WiringPi, you should not change the device tree since WringPi does use the 'gpio' framework. The device tree is for a device drivers in the kernel space. I believe you are able to use WiringPi to change the pin state and most/all pins would be able to work as expected.

If you concern is the default status of GPIO before running WiringPi, you must change the default state in U-boot. This is what you've tried at first if I remember correctly. What I am not sure as of now is if the GPIO pins set in U-boot keeps its state while Linux kernel loads and runs until your WiringPi based app starts. If you want to know more specific method, you can pick up one or two pins and we both can try to set.

One question, do you want to use WiringPi only to control GPIO or are you going to handle other pins like i2c or spi?
Yes. Changing the default state in U-boot is what i've tried at first.
Yes. I am using other features like i2c0 or uatr0.
And it would be great to make an example. I'm trying to output low the spi pins(19 - 21 - 23 - 24) now. could be these pins.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Wed Nov 04, 2020 12:00 am
tobetter wrote:
Tue Nov 03, 2020 8:16 pm
If you are going to use WiringPi, you should not change the device tree since WringPi does use the 'gpio' framework. The device tree is for a device drivers in the kernel space. I believe you are able to use WiringPi to change the pin state and most/all pins would be able to work as expected.

If you concern is the default status of GPIO before running WiringPi, you must change the default state in U-boot. This is what you've tried at first if I remember correctly. What I am not sure as of now is if the GPIO pins set in U-boot keeps its state while Linux kernel loads and runs until your WiringPi based app starts. If you want to know more specific method, you can pick up one or two pins and we both can try to set.

One question, do you want to use WiringPi only to control GPIO or are you going to handle other pins like i2c or spi?
Yes. Changing the default state in U-boot is what i've tried at first.
Does this work as you expected? If not, what does not work?
What did you change the code in U-boot?
Yes. I am using other features like i2c0 or uatr0.
Ok, keep "i2c0" and "uart0" in the line of overlays so that the device tree keeps creating the device node.
And it would be great to make an example. I'm trying to output low the spi pins(19 - 21 - 23 - 24) now. could be these pins.
Bad example...:) But, OK.
I think the pin 19 and pin 21 would be fine to control, but GPIOA_4 and GPIOX_10 would be not. If so, check if you have 'spi0' in the line of overlays and check if you have /dev/spi* after booting.

Can you manage the pin 13 (GPIOX_4) to control as you expected from U-boot to kernel?

Out of curiosity, since you said you are going to use i2c0 or uart0, are you able to control the bus without WiringPi, with native C functions?

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Re: Change pin state and value with u-boot.

Post by paulcrawford »

There is another way to change the pin state, or in my case I needed to change the default pull down resistors to pull ups for GPIOA.4 and GPIOA.12; all that is needed is the change the memory map as detailed in the wiki: https://wiki.odroid.com/odroid-n2/appli ... apped_gpio. I wrote a very small c program based on the wiki example and then compiled it. Then I wrote a small service to run the executable at startup. This ensures that I always have pull ups for 4 and 12.

This is the c program:

Code: Select all

#include <stdio.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <stdint.h>

#define	GPIO_REG_MAP            0xFF634000
#define GPIOX_FSEL_REG_OFFSET   0x116
#define GPIOX_OUTP_REG_OFFSET   0x117
#define GPIOX_INP_REG_OFFSET    0x118
#define PAD_PULL_UP_REG5_OFFSET 0x13F
#define BLOCK_SIZE              (4*1024)
static volatile uint32_t *gpio;

int main(int argc, char **argv) {
    int fd;

    if ((fd = open("/dev/gpiomem", O_RDWR | O_SYNC | O_CLOEXEC)) < 0) {
        printf("Unable to open /dev/gpiomem\n");
        return -1;
    }

    gpio = mmap(0, BLOCK_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, GPIO_REG_MAP);
    if (gpio < 0) {
        printf("Mmap failed.\n");
        return -1;
    }

    *(gpio + (PAD_PULL_UP_REG5_OFFSET)) |= (1 << 4);
    *(gpio + (PAD_PULL_UP_REG5_OFFSET)) |= (1 << 12);
    return 0;
}

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Re: Change pin state and value with u-boot.

Post by aress »

tobetter wrote:
Wed Nov 04, 2020 12:21 am
Does this work as you expected? If not, what does not work?
What did you change the code in U-boot?
i just add:

Code: Select all

gpio_direction_output(477, 1);
in board_init function to try.
tobetter wrote:
Wed Nov 04, 2020 12:21 am
Bad example...:) But, OK.
I think the pin 19 and pin 21 would be fine to control, but GPIOA_4 and GPIOX_10 would be not. If so, check if you have 'spi0' in the line of overlays and check if you have /dev/spi* after booting.
I checked spi0 from config.ini and terminal. it doesn't write in the config file and there is no /dev/spi*.
tobetter wrote:
Wed Nov 04, 2020 12:21 am
Can you manage the pin 13 (GPIOX_4) to control as you expected from U-boot to kernel?
I haven't done this before. And I don't know how to do this yet. i try the information i find but these are usually for RPI.
tobetter wrote:
Wed Nov 04, 2020 12:21 am
Out of curiosity, since you said you are going to use i2c0 or uart0, are you able to control the bus without WiringPi, with native C functions?
Yes, I did but I'd rather use it with WiringPi if possible
paulcrawford wrote:
Wed Nov 04, 2020 12:21 pm
There is another way to change the pin state, or in my case I needed to change the default pull down resistors to pull ups for GPIOA.4 and GPIOA.12; all that is needed is the change the memory map as detailed in the wiki: https://wiki.odroid.com/odroid-n2/appli ... apped_gpio. I wrote a very small c program based on the wiki example and then compiled it. Then I wrote a small service to run the executable at startup. This ensures that I always have pull ups for 4 and 12.

This is the c program:

Code: Select all

#include <stdio.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <stdint.h>

#define	GPIO_REG_MAP            0xFF634000
#define GPIOX_FSEL_REG_OFFSET   0x116
#define GPIOX_OUTP_REG_OFFSET   0x117
#define GPIOX_INP_REG_OFFSET    0x118
#define PAD_PULL_UP_REG5_OFFSET 0x13F
#define BLOCK_SIZE              (4*1024)
static volatile uint32_t *gpio;

int main(int argc, char **argv) {
    int fd;

    if ((fd = open("/dev/gpiomem", O_RDWR | O_SYNC | O_CLOEXEC)) < 0) {
        printf("Unable to open /dev/gpiomem\n");
        return -1;
    }

    gpio = mmap(0, BLOCK_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, GPIO_REG_MAP);
    if (gpio < 0) {
        printf("Mmap failed.\n");
        return -1;
    }

    *(gpio + (PAD_PULL_UP_REG5_OFFSET)) |= (1 << 4);
    *(gpio + (PAD_PULL_UP_REG5_OFFSET)) |= (1 << 12);
    return 0;
}
thanks but this is not what I want. At boot time, pins should output 0. otherwise the device connected to the pin becomes active.

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Re: Change pin state and value with u-boot.

Post by odroid »

odroid wrote:
Tue Oct 27, 2020 5:15 pm
Meanwhile, check the GPIO pin state on the u-boot stage with a USB-UART serial console cable.
You also need to disable the SPI boot to avoid any side effects.
Did you have a chance to check the GPIO state when before starting kernel?
Do you have a USB-UART cable to stop the kernel booting process and enter into u-boot prompt mode?

BTW, I think you just need an external pull-down resistor to make the signal output low until your gpio control software runs.

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Re: Change pin state and value with u-boot.

Post by tobetter »

You can try this code to test in U-boot, this code will set high as an example and you can change the code board_gpio_default(gpios, ARRAY_SIZE(gpios), 1); to set low. Please test and let us know which pin does to keep low on your end.

Code: Select all

diff --git a/board/hardkernel/odroidn2/odroidn2.c b/board/hardkernel/odroidn2/odroidn2.c
index ce3bd94..b31340d 100644
--- a/board/hardkernel/odroidn2/odroidn2.c
+++ b/board/hardkernel/odroidn2/odroidn2.c
@@ -341,10 +341,43 @@ U_BOOT_DEVICE(spifc) = {
 };
 #endif /* CONFIG_AML_SPIFC */
 
+static int gpios[] = {
+       GPIOX_0,
+       GPIOX_1,
+       GPIOX_2,
+       GPIOX_3,
+       GPIOX_4,
+       GPIOX_5,
+       GPIOX_6,
+       GPIOX_7,
+       GPIOX_8,
+       GPIOX_12,
+};
+
+static int board_gpio_default(int *gpios, int nr_gpios, int status)
+{
+       int i;
+       int gpio;
+
+       for (i = 0; i < nr_gpios; i++) {
+               gpio = GPIOEE(gpios[i]);
+               if (gpio_request(gpio, "gpio") < 0) {
+                       printf("failed to request GPIO pin %d\n", gpio);
+                       continue;
+               }
+
+               gpio_direction_output(gpio, status);
+       }
+
+       return 0;
+}
+
 int board_init(void)
 {
        board_led_alive(1);
 
+       board_gpio_default(gpios, ARRAY_SIZE(gpios), 1);
+
 #ifdef CONFIG_USB_XHCI_AMLOGIC_V2
        board_usb_pll_disable(&g_usb_config_GXL_skt);
        board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);

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Re: Change pin state and value with u-boot.

Post by aress »

odroid wrote:
Wed Nov 04, 2020 6:01 pm
Did you have a chance to check the GPIO state when before starting kernel?
Do you have a USB-UART cable to stop the kernel booting process and enter into u-boot prompt mode?
Yes, I have USB-UART cable. I haven't tried to stop the kernel booting process and enter into u-boot prompt mode. i wil try this.
odroid wrote:
Wed Nov 04, 2020 6:01 pm
BTW, I think you just need an external pull-down resistor to make the signal output low until your gpio control software runs.
so I need to change Memory Mapped GPIO with u-boot. I'll try this too.

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Re: Change pin state and value with u-boot.

Post by aress »

tobetter wrote:
Wed Nov 04, 2020 6:44 pm
You can try this code to test in U-boot, this code will set high as an example and you can change the code board_gpio_default(gpios, ARRAY_SIZE(gpios), 1); to set low. Please test and let us know which pin does to keep low on your end.

Code: Select all

diff --git a/board/hardkernel/odroidn2/odroidn2.c b/board/hardkernel/odroidn2/odroidn2.c
index ce3bd94..b31340d 100644
--- a/board/hardkernel/odroidn2/odroidn2.c
+++ b/board/hardkernel/odroidn2/odroidn2.c
@@ -341,10 +341,43 @@ U_BOOT_DEVICE(spifc) = {
 };
 #endif /* CONFIG_AML_SPIFC */
 
+static int gpios[] = {
+       GPIOX_0,
+       GPIOX_1,
+       GPIOX_2,
+       GPIOX_3,
+       GPIOX_4,
+       GPIOX_5,
+       GPIOX_6,
+       GPIOX_7,
+       GPIOX_8,
+       GPIOX_12,
+};
+
+static int board_gpio_default(int *gpios, int nr_gpios, int status)
+{
+       int i;
+       int gpio;
+
+       for (i = 0; i < nr_gpios; i++) {
+               gpio = GPIOEE(gpios[i]);
+               if (gpio_request(gpio, "gpio") < 0) {
+                       printf("failed to request GPIO pin %d\n", gpio);
+                       continue;
+               }
+
+               gpio_direction_output(gpio, status);
+       }
+
+       return 0;
+}
+
 int board_init(void)
 {
        board_led_alive(1);
 
+       board_gpio_default(gpios, ARRAY_SIZE(gpios), 1);
+
 #ifdef CONFIG_USB_XHCI_AMLOGIC_V2
        board_usb_pll_disable(&g_usb_config_GXL_skt);
        board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
Image
This way works for gpio pins with no features. what can i do for spi interface pins.

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Thu Nov 05, 2020 5:03 pm
tobetter wrote:
Wed Nov 04, 2020 6:44 pm
You can try this code to test in U-boot, this code will set high as an example and you can change the code board_gpio_default(gpios, ARRAY_SIZE(gpios), 1); to set low. Please test and let us know which pin does to keep low on your end.

Code: Select all

diff --git a/board/hardkernel/odroidn2/odroidn2.c b/board/hardkernel/odroidn2/odroidn2.c
index ce3bd94..b31340d 100644
--- a/board/hardkernel/odroidn2/odroidn2.c
+++ b/board/hardkernel/odroidn2/odroidn2.c
@@ -341,10 +341,43 @@ U_BOOT_DEVICE(spifc) = {
 };
 #endif /* CONFIG_AML_SPIFC */
 
+static int gpios[] = {
+       GPIOX_0,
+       GPIOX_1,
+       GPIOX_2,
+       GPIOX_3,
+       GPIOX_4,
+       GPIOX_5,
+       GPIOX_6,
+       GPIOX_7,
+       GPIOX_8,
+       GPIOX_12,
+};
+
+static int board_gpio_default(int *gpios, int nr_gpios, int status)
+{
+       int i;
+       int gpio;
+
+       for (i = 0; i < nr_gpios; i++) {
+               gpio = GPIOEE(gpios[i]);
+               if (gpio_request(gpio, "gpio") < 0) {
+                       printf("failed to request GPIO pin %d\n", gpio);
+                       continue;
+               }
+
+               gpio_direction_output(gpio, status);
+       }
+
+       return 0;
+}
+
 int board_init(void)
 {
        board_led_alive(1);
 
+       board_gpio_default(gpios, ARRAY_SIZE(gpios), 1);
+
 #ifdef CONFIG_USB_XHCI_AMLOGIC_V2
        board_usb_pll_disable(&g_usb_config_GXL_skt);
        board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
Image
This way works for gpio pins with no features. what can i do for spi interface pins.
You can add more pins to the array and test if such pins work as expected. Since you said you do not have /dev/spi*, such pins are not for SPI at all.

Code: Select all

GPIOX_9,
GPIOX_10,
GPIOX_11,
GPIOA_4

aress
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Re: Change pin state and value with u-boot.

Post by aress »

Sorry this is my mistake. I was working on spi. when i delete it from config.ini, it is worked.
Image
Thanks for your halp. :)

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Re: Change pin state and value with u-boot.

Post by tobetter »

aress wrote:
Thu Nov 05, 2020 5:18 pm
Sorry this is my mistake. I was working on spi. when i delete it from config.ini, it is worked.
Image
Thanks for your halp. :)
Ok, then all good? :)

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Re: Change pin state and value with u-boot.

Post by aress »

tobetter wrote:
Thu Nov 05, 2020 5:21 pm
Ok, then all good? :)
Yes all good. thanks again :)
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