Overclock RAM Speed

[sgudla]

Hi All,

I am trying to figure out a way to modify the RAM timing parameters like (tCL, tRAS, etc.). In desktops we can do this via BIOS. Is there any way to do this in android devices? Any leads will be of great help.

Thanks.

[sgudla]

The DRAM clock parameters exist in the Kernel DMC drivers and there is no simple way to change it like PC BIOS.
If you have enough Kernel development experience, you can search the DMC drivers in our Android source code.

Anyway, there is not much room to improve the DRAM throughput performance since LPDDR3 configuration has been already optimized.

[joy]

If you're planning to use android of XU4, you can refer to devfreq mif drivers (= exynos5422 DMC driver) in kernel 3.10.y.
https://github.com/hardkernel/linux/blo ... mif.c#L208
But, unfortunately we don't have any available material that describes internal registers to control tCL, RAS or CAS.

For kernel 4.14.y, there is no mif driver so far.
So we made an interface to control ram clocking on u-boot stage.
viewtopic.php?f=93&t=27117
https://wiki.odroid.com/odroid-xu4/appl ... _overclock

For kernel 5.x, I need to check it.

[joy]

@sgudla,
As odroid mentioned, we've already looked into the rooms and put some kinds of tests.
already optimized and overclocked.
You can check the history in this thread, too.
viewtopic.php?f=93&t=27117

[sgudla]

Hi,

Thank you for the replies. I was going through the link viewtopic.php?f=93&t=27117, i see that for XU4, @joy you have added 933MHz frequency.
In order to add a custom frequency, could you help me with the steps required? (if its possible).

PS: I am not looking to get the maximum performance, i am only looking for a way to change the latency values and by changing the frequency if we can achieve it, i wanted to know how to do it?

[sgudla]

Hi @joy,

In the link https://github.com/hardkernel/linux/blo ... mif.c#L208 for 933MHz there are 3 values as shown below:
{0x3D6BA816, 0x4742086E, 0x60670447}, /*933Mhz*/

I have a couple of questions on them:
1. How do we get these values?
2. do these values set some registers on the memory device?

I was going through the JEDEC spec for LPDDR5 and under the section Mode Register Definition - they have some registers defined to set tWL and tRL. Can these be programmed?

I am a newbie and trying to figure out how it works. Thank you for the help.

[joy]

Hi sgudla,

For the table, I found the values of timingRow, timingData and timingPower from one of existing Exynos mif drivers in kernel 3.10.y.
https://github.com/hardkernel/linux/blo ... if.c#L2399
So I have no idea how to configure the specific value of the registers.

I thought exynos5320 DMC IP may be from a same branch with exynos5422 because registers configurations are same
then, I did put various kinds of tests and confirmed it.

And as I mentioned, we don't have detailed materials and I think it may be samsung confidential parts.
I'm sorry I didn't help.