ODroid C2 + UPS3 won't power on when power returns

[Hertog]

Hi,

I use the script provided on the wiki to shut down the odroid once the voltage of the battery reaches 3.7V, however, once this is done, and power returns, the odroid will not power up again.
As it seems, the odroid does not go in full shutdown, but stays in a halt-state (red led still on).

My use-case is the following: I have the odroid + ups in my car. As soon as I start the car, power will be supplied to the UPS, which should turn on the odroid.
When I turn off the car, the odroid should stay powered for a while, power off gracefully, and then, when I start the car again, it should power up.

From the description on the UPS3-wiki ('When the AC power source becomes available again, the UPS3 will supply power to the ODROID again automatically.
'), I gathered that this would function in the way I described.

However, it does not.

It seems that I have no other option but to run down the power on the battery completely, greatly diminishing the lifetime of the battery.

Is there any way to make the UPS behave in a more useful (to me that is) way?

[odroid]

Right. The battery should be lower than 3.4Volt to restart the system automatically with external trigger. Sorry about that.
The battery pack has a deep-discharging protection circuit internally and the lifetime won't be affected.

Another possible workaround : Adding a simple(one-shot?) trigger circuit on SW1 pin 1-2 on UPS3.
viewtopic.php?f=115&t=22131&p=149307#p149286

[Hertog]

Good to know about the safety cut-off at 3.4 V. That might be sufficient.
Any idea how long it would take an idle ODroid that takes a full 30 minutes from battery full to 3.7V shutdown to go down to 3.4V (and hence trigger the real shutdown?)

Could you provide some hints as to how to create this simple trigger circuit? I'm a software guy, not a hardware one
The Odroid is to be my car media center, and I'll have hell to pay if, after a stopover > 30 minutes but shorter than the run down to 3.4V and thus the system would not be up (also I would mis out on all my OBD2 data which I want it to log).
Manually triggering it is not an option, since it's going to be tucked away somewhere in the car.

And lastly: would the UPS2 (after modification) function as intended on the C2?

[odroid]

I understood your situation.
But we may need a small MCU board like Arduino-Nano to detect the power line and make a trigger signal.
We will try to find a simpler solution.

[Hertog]

Does the POWER_LATCH perform any sensible function? (Or rather, should it do something, but it doesnt?)

[odroid]

POWER_LATCH is an input signal to keep enabling 5V output.
Refer the schematics.
http://odroid.com/dokuwiki/lib/exe/fetc ... rev0.1.pdf

[Hertog]

It doesn't seem to do very much, does it? If I understand correctly from the datasheet of the NCP380HMUAJAATBG, POWER_LATCH/EN should be enabled to have OUT enabled, however, no matter what is on EN, there is output on OUT, and thus on pin 1 and 2 of the odroid.

The board works perfectly fine without regard for the C1/C2-select switch, the odroid c2 starts up with the selector set to C1 even though on a C2 pin 15 (the POWER_LATCH pin for the C1) is low, and thus should not enable OUT, and no power should flow through PIN 1&2 (tested this with a LED).

Am I interpreting the datasheets wrongly? It's been aeons since I had to read this stuff, and I'm just getting back into it (and really liking it )

(Edit, warning, rambling): OK, from what I understand from the schematics, Since BAT_OK, AC_OK and LATCH_C2 are all connected to EN on SW1, and all three need to be 0 for the UPS3 to turn off, the reason power keeps being fed to PIN 1 & 2 is that removing power and setting C2_LATCH low does not pull MODE low, since it is still being fed from BAT_OK.

[odroid]

There are three input signals to the NCP380.
- AC_OK
- BAT_OK
- LATCH

It is a sort of Wired-OR combination.

[Hertog]

@Odroid, Thanks for sticking with me Really appreciate the time you take to answer my (probably obvious) questions

[CaISJoe]

Hi

This is a simple DCPlus circuit for correct restart :
http://cais-lpm.weebly.com/uploads/9/7/ ... erplus.pdf

[Hertog]

@CaISJoe, thanks!

[natenho]

I still don't understand what is the purpose of POWER_LATCH. Can someone please explain it? How does it work and which "problem" it solves?

[odroid]

POWER_LATCH is an output signal from C2. (Input on the UPS3)
If the POWER_LATCH level is low, UPS3 5Volt output is disabled.

[natenho]

ok, sorry, I'm a little confused here:

In the Auto shutdown script at http://odroid.com/dokuwiki/doku.php?id=en:odroid-ups3, shouldn't be a line setting LATCH pin to 0?
I've made a couple of tests and the red LED only turned off when I've added the following line to the script:

Code: Select all

if [ $retval -eq 0 ]
then
      echo "battery is lower than 3.7V"
      halt
                #Added the line bellow to set LATCH to LOW
      gpio_setvalue $LATCH_GPIO 0
else
      echo "battery is good"
fi

When I plug UPS3 into A/C, it turns on and boot up the system only when I set LATCH to 0 after halt. When LATCH is left 1, the board keeps red LED on.
By the way, I don't get how it works after power off, I mean, how does LATCH pin change the behavior of UPS3 even when C1/C2 is powered off??

[odroid]

This is our basic concept.
The original script keeps the C2/C1 alive in halt mode and it drains the battery.
Once the battery is out and the AC power comes again, it will boot automatically.
So your observation is normal.

If the period of power failure is too short, you have to turn the ODROID on manually.

[natenho]

Great, I think I'm almost there. Thanks for your patience. More questions:

If the POWER_LATCH level is low, UPS3 5Volt output is disabled.

1) In this case, shouldn't setting POWER_LATCH=0 actually have interrupted the board power?

If the period of power failure is too short, you have to turn the ODROID on manually.

2) I understand the "short power failure issue", because the system will enter in halt mode, then, as a result of race condition, the AC will start charging the battery and the board will never get the red led off. But.... isn't the latch pin responsible for solving that? It's being hard to understand it's purpose, it seems simple, but still I don't get it!

3) When the system is halted with LATCH=0, the board keeps rebooting. Won't it damage the SD card?

4) After all, what I need to understand is how to setup the system (afaik, the latch pin) to achieve the following:
Premise: The board won't be powered off unless battery is low.
- The board must shutdown gracefully when AC is gone but only if the battery is low (red led must be off).
- The board must boot up automatically when AC comes again (hence the need of red led off).

[ruppi]

Hi natenho,

Below we have answered the questions.

1) Use "shutdown" instead of "halt".
/sbin/shutdown command is actually set to POWER_LATCH=0

2)
For that reason, the script was registered in crontab to run the script every two minutes.
If you are concerned, you may want to increase the running time of the script.
3)
If you use shutdown instead of the halt command, the LATCH will be LOW after normal power off.

4)
The above will be able to find the answer.

BR
Ruppi

[natenho]

Hello! Thank you for your time,

1) I'm not running the original odroid C1 image, actually I'm running on a custom buildroot based linux 3.10.80 image with busybox, which doesn't have /sbin/shutdown.
How does /sbin/shutdown know about POWER_LATCH? I mean, it's a proprietary hardkernel's ups3 feature, isn't it?

2) I suppose I didn't make myself clear. I would like to understand the purpose of power_latch pin and why it is important, why does it exist? There is no documentation about it, only that wiki I mentioned before. To be honest, the question 2) remains unanswered

3) If I could understand the behaviors tied to power_latch pin, it would be easier to understand everything else. Btw, q 3) is still unanswered

4) 1), 2) and 3) can definitely answer it.

[odroid]

1. The "shutdown" command was included in Canonical's Ubuntu.
I think you can find the source code of shutdown in Canonical's repo.
The "shutdown" process is not directly related to the power_latch control.
The "shutdown" process stops running the Kernel and jumps to the u-boot and stays in the lowest power mode with the default GPIO level.
We will check how to implement a similar process on the buildroot.

2. If the power_latch pin is low, the output voltage from UPS3 can be zero once AC_OK & BAT_OK are low. (As I told you, they 3 inputs are Wired-OR)
If this explanation is not understandable, please ask us again.

[Brian.K]

Please use poweroff command instead of halt. halt does not execute the poweroff routine in the kernel side.