Odroid M1 I2S output

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mctom
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Odroid M1 I2S output

Post by mctom »

I checked the shop information and the wiki, I can't find any way to enable I2S audio output.
Is this just a matter of device tree magic, or this feature is not supported at all?
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Re: Odroid M1 I2S output

Post by odroid »

We have no plan to test/support the I2S interface on the M1 platform at this moment.
I think the on-board analog output sound quality is better than many of generic I2S add-on boards in the market.
We measured the sound quality with the Audio Precision equipment. https://www.ap.com/analyzers-accessories/apx515/

Frankly speaking, its sound quality was not distinguishable against our pricey HiFi-Shield. ;)
https://www.hardkernel.com/shop/hifi-shield-plus/
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Re: Odroid M1 I2S output

Post by mctom »

But I just wanted to test my FPGA code with a real I2S signal. ;) No worries, I can use some other Odroid for that.

For me, any THD+N below 1% is fine ;)
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Re: Odroid M1 I2S output

Post by mctom »

I heard what you said that HK does not plan to test or maintain such functionality, but I'm sure the community support would be welcome.
Given this, it should be said that I2S support should be doable, as necessary pins are routed to GPIO header (Coincidence? :roll: ). Maybe not today, but I may need that I2S connectivity in my future project.
The question is, is that only a matter of crafting an overlay, or does that involve work in kernel code?


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Re: Odroid M1 I2S output

Post by multiblitz »

I could not agree more !!!

I bought the M1 as HIghend Music Server for my external R2R DAC which is a complete different league from anything you have included here.

Sofar I use USB-OUtput, but original I2S directly from the Rockchip...that would be great !!

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Re: Odroid M1 I2S output

Post by mctom »

I did some poking around the device tree sources and I figured out as much:

- I2S1 on RK3568 has selectable output groups called M0 and M1, on different physical pins
- M1 is the group available on GPIO and doesn't collide with any other special pin functions
- M0 is in fact enabled by default, and physically routed to RK809 - the companion chip that among other things drives headphones and speaker outputs
- It may be fairly easy to craft an overlay that:
-- Reroutes I2S to M1 pins (in &i2s1_8ch/pinctrl-0)
-- Disables RK809 parts (rk809_sound and rk809_codec)
-- Enables some other driver in return.

Or maybe just routing the signal to M1 pins without trying to disable audio part of RK809 would be sufficient to get the basic I2S signal out from these pins?

The problem is, I can't play with this idea any further without a spare M1 for testing :?
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Re: Odroid M1 I2S output

Post by joerg »

I am trying to enable the Hifishield2 on kernel 6.8.6. After some corrections in the devicetree, now the driver for pcm5242 (pcm512x) starts without error and I see the card in Alsa.

Code: Select all

Welcome to Ubuntu 23.10 (GNU/Linux 6.8.6-odroid-arm64 aarch64

Code: Select all

joerg@server:~$ sudo aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: HDMI [HDMI], device 0: fe400000.i2s-i2s-hifi i2s-hifi-0 [fe400000.i2s-i2s-hifi i2s-hifi-0]
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: I2SSOC [I2S_SOC], device 0: fe410000.i2s-pcm512x-hifi pcm512x-hifi-0 [fe410000.i2s-pcm512x-hifi pcm512x-hifi-0]
  Subdevices: 1/1
  Subdevice #0: subdevice #0
But I dont have audio output with speaker-test: sudo speaker-test -c 2 -D hw:CARD=I2SSOC :(
And yes, @mctom, it is the pin configuration you have figured out.
I will do some more tests and maybe I have to use my oscilloscope...
Devicetree:

Code: Select all

&i2c3 {
	pinctrl-0 = <&i2c3m1_xfer>;
	status = "okay";

	pcm5242: pcm5242@4c {
		compatible = "ti,pcm5142";
		reg = <0x4c>;
		#sound-dai-cells = <0>;
		AVDD-supply = <&vcc3v3_sys>;
		DVDD-supply = <&vcc3v3_sys>;
		CPVDD-supply = <&vcc3v3_sys>;

	};
};

Code: Select all

	i2s-sound {
		compatible = "simple-audio-card";
		pinctrl-names = "default";
		simple-audio-card,name = "I2S_SOC";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,widgets =
			"Line", "Lineout";
		simple-audio-card,routing =
			"Lineout", "OUTL",
			"Lineout", "OUTR";

		simple-audio-card,cpu {
			sound-dai = <&i2s1_8ch>;
		};

		simple-audio-card,codec {
			sound-dai = <&pcm5242>;
		};
	};

Code: Select all

&i2s1_8ch {
	pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_mclk
			     &i2s1m1_lrcktx &i2s1m1_sdo0>;

//			     &i2s1m1_sdi0   &i2s1m1_sdi1
//			     &i2s1m1_sdi2   &i2s1m1_sdi3
//			     &i2s1m1_sdo0   &i2s1m1_sdo1
//			     &i2s1m1_sdo2   &i2s1m1_sdo3>;
	status = "okay";
};
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Re: Odroid M1 I2S output

Post by mctom »

That's a great step nevertheless, looking forward for the ultimate success. :)
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Re: Odroid M1 I2S output

Post by joerg »

I can see on my oscilloscope SCK about 3.07Mhz always, with speaker-test LRCK about 48kHz, and always some bits in DO after LRCK has changed. But I don't see clock in BCK! So I assume that devicetree isn't configured well. :(
And there is also this error in dmesg:

Code: Select all

pcm512x 0-004c: No SCLK, using BCLK: -2

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Re: Odroid M1 I2S output

Post by joerg »

When I add this

Code: Select all

		clocks = <&cru I2S1_MCLKOUT_TX>;
		clock-names = "mclk";
or this

Code: Select all

		clocks = <&cru MCLK_I2S1_8CH_TX>;
		clock-names = "mclk";
to the i2c3 / pcm5242 node, there is no error anymore, but still no clock on MCLK / BCLK and still silence...
I become out of ideas. :x

This is the connection:
Hifishield 2 = HS2

Code: Select all

HS2 pin 4 MCLK -> M1 pin 16 (GPIO3C.6)(I2S1_MCLK_M1)
HS2 pin 5 LRCK -> M1 pin 12 (GPIO3D.0)(I2S1_LRCK_TX_M1)
HS2 pin 6 SCLK -> M1 pin 18 (GPIO3C.7)(I2S1_SCLK_TX_M1)
HS2 pin 7 OUT  -> M1 pin 22 (GPIO3D.1)(I2S1_SD0_M1)
BTW, I see in the hifishield2 overlay of @tobetter in kernel odroid-5.15.y this:

Code: Select all

		target = <&tdmif_b>;

		__overlay__ {
			status = "okay";

			pinctrl-0 = <&mclk0_ao_pins>,
				<&tdm_ao_b_fs_pins>,
				<&tdm_ao_b_sclk_pins>,
				<&tdm_ao_b_dout0_pins>;

			pinctrl-names = "default";

			assigned-clocks = <&clkc_audio AUD_CLKID_TDM_MCLK_PAD0>,
				<&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>,
				<&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>;
			assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
				<&clkc_audio AUD_CLKID_MST_B_SCLK>,
				<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
			assigned-clock-rates = <0>, <0>, <0>;
		};
	};
Would I need to adapt it to M1 in same manner?

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Re: Odroid M1 I2S output

Post by mctom »

There are many more things I don't understand about it that I'm sure of, but here are some of my random ideas:

- Perhaps if you connected DAC's I2C wires as well, the driver would behave differently? I hope you didn't forget the GND and VCC wires. :)
- Is there any MCLK if you disconnect it from your Hifi Shield?
- Internet says that this error message is not an error. I found a few separate claims of that, this is one of them:
https://github.com/mikebrady/shairport-sync/issues/557
- I can't see the connection between i2c3m1 and I2S MCLK. Are you sure this is the clock that I2C node expects?
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Re: Odroid M1 I2S output

Post by joerg »

Of course I connected I2C wires and 3.3V and 5V and GND. Without the driver don't find the chip reports error and does not probe.
And no MCLK, also when it is disconnected.
And what it is i2c3m1?
Yes, this is not an error, and doesn't result in dead driver. The sound card is still there.

Code: Select all

	if (IS_ERR(pcm512x->sclk)) {
		dev_info(dev, "No SCLK, using BCLK: %ld\n",
			 PTR_ERR(pcm512x->sclk));

		/* Disable reporting of missing SCLK as an error */
		regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
				   PCM512x_IDCH, PCM512x_IDCH);

		/* Switch PLL input to BCLK */
		regmap_update_bits(regmap, PCM512x_PLL_REF,
				   PCM512x_SREF, PCM512x_SREF_BCK);
	}

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Re: Odroid M1 I2S output

Post by mctom »

joerg wrote:
Tue Jun 11, 2024 10:34 pm
And what it is i2c3m1?
I meant this:
joerg wrote:
Tue Jun 11, 2024 9:18 pm
When I add this

clocks = <&cru I2S1_MCLKOUT_TX>;
clock-names = "mclk";

or this

clocks = <&cru MCLK_I2S1_8CH_TX>;
clock-names = "mclk";

to the i2c3 / pcm5242 node
I didon't understand why i2c3 node gets I2S clock.. But I have found a similar example in rk3588-evb1-lp4.dtsi, and I think this is an input to a sound driver rather than I2C port:

Code: Select all

 497   │ &i2c7 {
 498   │     status = "okay";
 499   │     es8388: es8388@11 {
 500   │         status = "okay";
 501   │         #sound-dai-cells = <0>;
 502   │         compatible = "everest,es8388", "everest,es8323";
 503   │         reg = <0x11>;
 504   │         clocks = <&mclkout_i2s0>;
 505   │         clock-names = "mclk";
 506   │         assigned-clocks = <&mclkout_i2s0>;
 507   │         assigned-clock-rates = <12288000>;
 508   │         pinctrl-names = "default";
 509   │         pinctrl-0 = <&i2s0_mclk>;
 510   │     };
 511   │ };
Are you able to post the whole device tree source file that you created?
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Re: Odroid M1 I2S output

Post by joerg »

Of course. With this devicetree there are no errors, a sound card I2SS_SOC and signals on SCLK, LRCK, SDO0, as explained above. I have disabled i2s hdmi, because for testing I only want to have one sound card.

Code: Select all

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Hardkernel Co., Ltd.
 *
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"

/ {
	model = "Hardkernel ODROID-M1";
	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
		i2c0 = &i2c3;
		i2c3 = &i2c0;
		mmc0 = &sdhci;
		mmc1 = &sdmmc0;
		serial0 = &uart1;
		serial1 = &uart0;
	};

	chosen {
		stdout-path = "serial2:1500000n8";
	};

	dc_12v: dc-12v-regulator {
		compatible = "regulator-fixed";
		regulator-name = "dc_12v";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
	};

	hdmi-con {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_in: endpoint {
				remote-endpoint = <&hdmi_out_con>;
			};
		};
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ir_receiver_pin>;
	};

	leds {
		compatible = "gpio-leds";

		led_power: led-0 {
			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_RED>;
			default-state = "keep";
			linux,default-trigger = "default-on";
			pinctrl-names = "default";
			pinctrl-0 = <&led_power_pin>;
		};
		led_work: led-1 {
			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_HEARTBEAT;
			color = <LED_COLOR_ID_BLUE>;
			linux,default-trigger = "heartbeat";
			pinctrl-names = "default";
			pinctrl-0 = <&led_work_pin>;
		};
	};

	/*rk809-sound {
		compatible = "simple-audio-card";
		pinctrl-names = "default";
		pinctrl-0 = <&hp_det_pin>;
		simple-audio-card,name = "Analog RK817";
		simple-audio-card,format = "i2s";
		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,widgets =
			"Headphone", "Headphones",
			"Speaker", "Speaker";
		simple-audio-card,routing =
			"Headphones", "HPOL",
			"Headphones", "HPOR",
			"Speaker", "SPKO";

		simple-audio-card,cpu {
			sound-dai = <&i2s1_8ch>;
		};

		simple-audio-card,codec {
			sound-dai = <&rk809>;
		};
	};*/

	i2s-sound {
		compatible = "simple-audio-card";
		pinctrl-names = "default";
		simple-audio-card,name = "I2S_SOC";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,bitclock-master = <&sndcpu>;
		simple-audio-card,frame-master = <&sndcpu>;
		//simple-audio-card,bitclock-inversion;
		simple-audio-card,widgets =
			"Headphone", "Headphones";
		simple-audio-card,routing =
			"Headphones", "OUTL",
			"Headphones", "OUTR";

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&i2s1_8ch>;
		};

		sndcodec: simple-audio-card,codec {
			sound-dai = <&pcm5242>;
		};
	};

	rk3568-gpiomem {
		compatible = "rockchip,rk3568-gpiomem";
		reg= <0x0 0xfd660000 0x0 0x1000>;
		status = "okay";
	};

	vcc3v3_pcie: vcc3v3-pcie-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_pcie";
		enable-active-high;
		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <5000>;
		vin-supply = <&vcc3v3_sys>;
	};

	vcc3v3_sys: vcc3v3-sys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&dc_12v>;
	};

	vcc5v0_sys: vcc5v0-sys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&dc_12v>;
	};

	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_usb_host";
		enable-active-high;
		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_usb_otg";
		enable-active-high;
		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc5v0_sys>;
	};
};

&combphy0 {
	/* Used for USB3 */
	phy-supply = <&vcc5v0_usb_host>;
	status = "okay";
};

&combphy1 {
	/* Used for USB3 */
	phy-supply = <&vcc5v0_usb_otg>;
	status = "okay";
};

&combphy2 {
	/* used for SATA */
	status = "okay";
};

&cpu0 {
	cpu-supply = <&vdd_cpu>;
};

&cpu1 {
	cpu-supply = <&vdd_cpu>;
};

&cpu2 {
	cpu-supply = <&vdd_cpu>;
};

&cpu3 {
	cpu-supply = <&vdd_cpu>;
};

&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy0>;
	phy-mode = "rgmii";
	phy-supply = <&vcc3v3_sys>;
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;
	status = "okay";

	tx_delay = <0x4f>;
	rx_delay = <0x2d>;
};

&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
};

&hdmi {
	avdd-0v9-supply = <&vdda0v9_image>;
	avdd-1v8-supply = <&vcca1v8_image>;
	status = "okay";
};

&hdmi_in {
	hdmi_in_vp0: endpoint {
		remote-endpoint = <&vp0_out_hdmi>;
	};
};

&hdmi_out {
	hdmi_out_con: endpoint {
		remote-endpoint = <&hdmi_con_in>;
	};
};

&hdmi_sound {
	status = "okay";
};

&i2c0 {
	status = "okay";

	vdd_cpu: regulator@1c {
		compatible = "tcs,tcs4525";
		reg = <0x1c>;
		fcs,suspend-voltage-selector = <1>;
		regulator-name = "vdd_cpu";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <800000>;
		regulator-max-microvolt = <1150000>;
		regulator-ramp-delay = <2300>;
		vin-supply = <&vcc3v3_sys>;

		regulator-state-mem {
			regulator-off-in-suspend;
		};
	};

	rk809: pmic@20 {
		compatible = "rockchip,rk809";
		reg = <0x20>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
		#clock-cells = <1>;
		clock-names = "mclk";
		clocks = <&cru I2S1_MCLKOUT_TX>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
		rockchip,system-power-controller;
		#sound-dai-cells = <0>;
		vcc1-supply = <&vcc3v3_sys>;
		vcc2-supply = <&vcc3v3_sys>;
		vcc3-supply = <&vcc3v3_sys>;
		vcc4-supply = <&vcc3v3_sys>;
		vcc5-supply = <&vcc3v3_sys>;
		vcc6-supply = <&vcc3v3_sys>;
		vcc7-supply = <&vcc3v3_sys>;
		vcc8-supply = <&vcc3v3_sys>;
		vcc9-supply = <&vcc3v3_sys>;
		wakeup-source;

		regulators {
			vdd_logic: DCDC_REG1 {
				regulator-name = "vdd_logic";
				regulator-always-on;
				regulator-boot-on;
				regulator-initial-mode = <0x2>;
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <6001>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_gpu: DCDC_REG2 {
				regulator-name = "vdd_gpu";
				regulator-always-on;
				regulator-initial-mode = <0x2>;
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <6001>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_ddr: DCDC_REG3 {
				regulator-name = "vcc_ddr";
				regulator-always-on;
				regulator-boot-on;
				regulator-initial-mode = <0x2>;

				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vdd_npu: DCDC_REG4 {
				regulator-name = "vdd_npu";
				regulator-initial-mode = <0x2>;
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <6001>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_1v8: DCDC_REG5 {
				regulator-name = "vcc_1v8";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdda0v9_image: LDO_REG1 {
				regulator-name = "vdda0v9_image";
				regulator-always-on;
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdda_0v9: LDO_REG2 {
				regulator-name = "vdda_0v9";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdda0v9_pmu: LDO_REG3 {
				regulator-name = "vdda0v9_pmu";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <900000>;
				};
			};

			vccio_acodec: LDO_REG4 {
				regulator-name = "vccio_acodec";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vccio_sd: LDO_REG5 {
				regulator-name = "vccio_sd";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc3v3_pmu: LDO_REG6 {
				regulator-name = "vcc3v3_pmu";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vcca_1v8: LDO_REG7 {
				regulator-name = "vcca_1v8";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcca1v8_pmu: LDO_REG8 {
				regulator-name = "vcca1v8_pmu";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcca1v8_image: LDO_REG9 {
				regulator-name = "vcca1v8_image";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_3v3: SWITCH_REG1 {
				regulator-name = "vcc_3v3";
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc3v3_sd: SWITCH_REG2 {
				regulator-name = "vcc3v3_sd";

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};
		};
	};
};

/*
&i2s0_8ch {
	status = "okay";
};
*/

&i2s1_8ch {
	pinctrl-0 = < &i2s1m1_mclk  &i2s1m1_lrcktx
			      &i2s1m1_sclktx &i2s1m1_sdo0>;
	status = "okay";
};

&i2c3 {
	pinctrl-0 = <&i2c3m1_xfer>;
	status = "okay";
	pcm5242: pcm5242@4c {
		compatible = "ti,pcm5142";
		reg = <0x4c>;
		clocks = <&cru I2S1_MCLKOUT_TX>;
		clock-names = "mclk";
		#sound-dai-cells = <0>;
		AVDD-supply = <&vcc3v3_sys>;
		DVDD-supply = <&vcc3v3_sys>;
		CPVDD-supply = <&vcc3v3_sys>;
		status = "okay";
	};
};

&mdio0 {
	rgmii_phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x0>;
		reset-assert-us = <20000>;
		reset-deassert-us = <100000>;
		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
	};
};

&pcie30phy {
	status = "okay";
};

&pcie3x2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_reset_pin>;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pinctrl {
	fspi {
		fspi_dual_io_pins: fspi-dual-io-pins {
			rockchip,pins =
				/* fspi_clk */
				<1 RK_PD0 1 &pcfg_pull_none>,
				/* fspi_cs0n */
				<1 RK_PD3 1 &pcfg_pull_none>,
				/* fspi_d0 */
				<1 RK_PD1 1 &pcfg_pull_none>,
				/* fspi_d1 */
				<1 RK_PD2 1 &pcfg_pull_none>;
		};
	};

	ir-receiver {
		ir_receiver_pin: ir-receiver-pin {
			/* external pullup to VCC3V3_SYS */
			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	leds {
		led_power_pin: led-power-pin {
			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
		led_work_pin: led-work-pin {
			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pcie {
		pcie_reset_pin: pcie-reset-pin {
			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		pmic_int_l: pmic-int-l {
			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	rk809 {
		hp_det_pin: hp-det-pin {
			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	usb {
		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pmu_io_domains {
	pmuio1-supply = <&vcc3v3_pmu>;
	pmuio2-supply = <&vcc3v3_pmu>;
	vccio1-supply = <&vccio_acodec>;
	vccio2-supply = <&vcc_1v8>;
	vccio3-supply = <&vccio_sd>;
	vccio4-supply = <&vcc_1v8>;
	vccio5-supply = <&vcc_3v3>;
	vccio6-supply = <&vcc_3v3>;
	vccio7-supply = <&vcc_3v3>;
	status = "okay";
};

&saradc {
	vref-supply = <&vcca_1v8>;
	status = "okay";
};

&sata2 {
	status = "okay";
};

&sdhci {
	bus-width = <8>;
	max-frequency = <200000000>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vcc_1v8>;
	status = "okay";
};

&sdmmc0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
	sd-uhs-sdr50;
	vmmc-supply = <&vcc3v3_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
};

&sfc {
	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
	pinctrl-0 = <&fspi_dual_io_pins>;
	pinctrl-names = "default";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;
		spi-rx-bus-width = <2>;
		spi-tx-bus-width = <1>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "SPL";
				reg = <0x0 0xe0000>;
			};
			partition@e0000 {
				label = "U-Boot Env";
				reg = <0xe0000 0x20000>;
			};
			partition@100000 {
				label = "U-Boot";
				reg = <0x100000 0x200000>;
			};
			partition@300000 {
				label = "splash";
				reg = <0x300000 0x100000>;
			};
			partition@400000 {
				label = "Filesystem";
				reg = <0x400000 0xc00000>;
			};
		};
	};
};

&tsadc {
	rockchip,hw-tshut-mode = <1>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
};

&uart2 {
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host0_ohci {
	status = "okay";
};

&usb_host0_xhci {
	dr_mode = "host";
	status = "okay";
};

&usb_host1_ehci {
	status = "okay";
};

&usb_host1_ohci {
	status = "okay";
};

&usb_host1_xhci {
	status = "okay";
};

&usb2phy0 {
	status = "okay";
};

&usb2phy0_host {
	phy-supply = <&vcc5v0_usb_host>;
	status = "okay";
};

&usb2phy0_otg {
	phy-supply = <&vcc5v0_usb_otg>;
	status = "okay";
};

&usb2phy1 {
	status = "okay";
};

&usb2phy1_host {
	phy-supply = <&vcc5v0_usb_host>;
	status = "okay";
};

&usb2phy1_otg {
	phy-supply = <&vcc5v0_usb_host>;
	status = "okay";
};

&vop {
	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&vp0 {
	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
		remote-endpoint = <&hdmi_in_vp0>;
	};
};

User avatar
joerg
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Re: Odroid M1 I2S output

Post by joerg »

And maybe do I have to create a conf like this two?

Code: Select all

ls -la /usr/share/alsa/cards
-rw-r--r-- 1 root root  998 Jan 20 11:39 rockchip-hdmi0.conf
-rw-r--r-- 1 root root  446 Jan 20 11:39 rockchip-rk809.conf
I think they are installed with odroid-alsa.

Code: Select all

cat /usr/share/alsa/cards/rockchip-hdmi0.conf
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2022 Hardkernel Co., Ltd.

<confdir:pcm/hdmi.conf>

rockchip-hdmi0.pcm.hdmi.0 {
        @args [ CARD AES0 AES1 AES2 AES3 ]
        @args.CARD { type string }
        @args.AES0 { type integer }
        @args.AES1 { type integer }
        @args.AES2 { type integer }
        @args.AES3 { type integer }
        type hooks
        slave.pcm {
                type hw
                card $CARD
                device 0
                subdevice 0
        }
        hooks.0 {
                type ctl_elems
                hook_args [
                        {
                                interface MIXER
                                name "IEC958 Playback Default"
                                lock true
                                preserve true
                                optional true
                                value [ $AES0 $AES1 $AES2 $AES3 ]
                        }
                ]
        }
        hint.device 0
}

Code: Select all

cat /usr/share/alsa/cards/rockchip-rk809.conf
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2022 Hardkernel Co., Ltd.

<confdir:pcm/front.conf>

rockchip-rk809.pcm.front.0 {
        @args [ CARD ]
        @args.CARD {
		type string
	}
	type hooks
	slave.pcm {
		type hw
		card $CARD
		device 0
	}
	hooks.0 {
		type ctl_elems
		hook_args [
			{ name "Playback Path" value 6 }
			# 0: OFF 1: RCV 2: SPK 3: HP 4: HP_NO_MIC 5: BT
			# 6: SPK_HP 7: RING_SPK 8: RING_HP 9: RING_HP_NO
		]
	}
}
The i2s soc is:

Code: Select all

sudo aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: I2SSOC [I2S_SOC], device 0: fe410000.i2s-pcm512x-hifi pcm512x-hifi-0 [fe410000.i2s-pcm512x-hifi pcm512x-hifi-0]
  Subdevices: 1/1
  Subdevice #0: subdevice #0

Code: Select all

sudo aplay -L
null
    Discard all samples (playback) or generate zero samples (capture)
hw:CARD=I2SSOC,DEV=0
    I2S_SOC, fe410000.i2s-pcm512x-hifi pcm512x-hifi-0
    Direct hardware device without any conversions
plughw:CARD=I2SSOC,DEV=0
    I2S_SOC, fe410000.i2s-pcm512x-hifi pcm512x-hifi-0
    Hardware device with all software conversions
sysdefault:CARD=I2SSOC
    I2S_SOC, fe410000.i2s-pcm512x-hifi pcm512x-hifi-0
    Default Audio Device
dmix:CARD=I2SSOC,DEV=0
    I2S_SOC, fe410000.i2s-pcm512x-hifi pcm512x-hifi-0
    Direct sample mixing device
I am a totally noob with this. :(

What would be the name of such a conf file? pcm512x-hifi-0.conf?

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mctom
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Re: Odroid M1 I2S output

Post by mctom »

Hold on, a realization has dawned on me.

Let me make a little glossary because it's getting confusing.

I2S standard specifies only three signals:
- SCK, a Serial Clock, also known as Bit Clock BCK,
- WS, Word Select, which indicates left or right channel, hence known as Left Right Clock LRCK
- SD, or Serial Data.

Wikipedia says:
Master clock (typically 256 x LRCLK)

This is not part of the I2S standard,[5] but is commonly included for synchronizing the internal operation of the analog/digital converters.[4][6]
Let's assume we call it MCK.

The confusing part is that PCM chip datasheet and driver call these pins differently.
By standards, Serial Clock SCK signal goes into BCK pin (referred to as BCLK in the driver code).
Similarly, Master Clock MCK signal should go into SCK pin, otherwise known as SCLK in driver's code.
Super confusing, but let's move on.

You have reported a 48kHz LRCK which is awesome.
You also said that SCK is at 3.07MHz, which is clearly 48kHz * 32 * 2, a valid bit clock in 32-bit mode.

PCM5242 has a capability to synthesize its own Master clock in case it's missing, by multiplying SCK (=BCK) frequency through the internal PLL. In fact 3.072 MHz is implicitly listed as a valid BCK frequency for 48kHz audio.

In absence of MCK, it rightfully switches to SCK clock source, which it states in its own convoluted way.

The driver code stub that you included suggests it does configure the internal PLL. I investigated the code myself and indeed it has a capability to calculate correct PLL settings, so I assume it does that.
If it failed, it should have dropped a message: "Impossible to generate a suitable SCK" or one of many other predefined errors.

In conclusion, I think that the device tree is fine and the chip should be working.
Perhaps this has always worked like that even with the official HK support on C-series?

Hardware-wise, there is only one thing that can mute the sound: Hifishield2 pin 11 pulled to GND.
Otherwise I think it should be a matter of system configuration.

EDIT:
I have found Documentation/devicetree/bindings/sound/pcm512x.txt:
- clocks : A clock specifier for the clock connected as SCLK. If this
is absent the device will be configured to clock from BCLK. If pll-in
and pll-out are specified in addition to a clock, the device is
configured to accept clock input on a specified gpio pin.
So in fact without specifying the "clocks" it has greater chances of success.
And your diagnosis is right, MCK doesn't work for a mysterious reason.
Punk ain't no religious cult, punk means thinking for yourself!
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joerg
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Re: Odroid M1 I2S output

Post by joerg »

Thank you for your input. HS2 pin 11 I left open and as of schematic it is pulled up. And yes the actual value is 3.3V.
All of the connections you listed above I have tried already!
But if it is 3 signal I2S or 4 signal I2S, that is the question. When we look at all C2 or C4 schematics, Hifishield2 schematic and also all devicetree configuration, then we see that HK has always used 4 signal I2S with PCM5242. On the other hand, all example configurations from M1 RK3568 Datasheet show only 3 signal I2S.
So, when I can start speaker-test without error, but there is silence, yes it seems to be Alsa configuration.
But what you think about simple-audio-card,widget and ,routing in devicetree? Can there be the culprit?
A very good essay about can be read here: https://bootlin.com/doc/training/audio/audio-slides.pdf

User avatar
joerg
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Re: Odroid M1 I2S output

Post by joerg »

I have tried to install on my C4 bullseye image with kernel 5.15 of @tobetter where there is also an overlay hifishield2. To compare and measure. But I can't make it work. It's not present on i2c bus. So I wonder if ever someone has tried it?
pcm512x 0-004c: Failed to reset device: -6
I am with this now all the day busy without success. Now I am waiting some input from whoever to go on.

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Re: Odroid M1 I2S output

Post by mctom »

Thank you for your dedication to this matter.

Yes, I was thinking about running Hifishield2 with a known working configuration just to see if MCK is really there. I expect frequency being a multiple of SCK, from 6.x MHz up to 50MHz.
I read somewhere that MCK may be present only when playing audio - which isn't what we want but I think I saw it stated somewhere in the device tree docs.

If all example configurations of RK3568 do not use MCLK then there is a possibility it simply doesn't work. Maybe Linux drivers don't support it?
For me it's not an issue because the DAC I want to use has 3-pin I2S interface, and your work had already been tremendously helpful.

About "widget" and "routing", as far as I can tell these are the fields that appear in alsamixer. I think these might be optional, to assign better looking names to parameters that will show up anyway. I would see what alsamixer does if these fields are removed. Improperly filled fields might be a cause of trouble, but I'm only guessing.
By the way, please check if your sound isn't muted in alsamixer, this happened to me once. :)
joerg wrote:
Wed Jun 12, 2024 5:07 am
pcm512x 0-004c: Failed to reset device: -6
I looked into the driver code and it seems this error may occur if I2C doesn't work. It is issued after the first attempt at communicating with the chip. Also reset is the first thing to do when talking to a chip.
I also found a definition of error -6, which seems to confirm my theory:
https://github.com/torvalds/linux/blob/ ... 0C1-L10C50
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Re: Odroid M1 I2S output

Post by joerg »

I am not sure if my Hifishield2 is functional. I have now enabled it on LineageOS21 for C2 and I can see on MCLK about 12.288Mhz, on SLCK 3.07Mhz, on LRCLK 48kHz and traffic on DO0. But I have silence. When I connect the Hifishield2 SPDIF to my speakers, I have sound. I use the same cinch cable to connect to Hifishield2 or to SPDIF converter, so it's not my cables or my amplifier.
The only way to be sure, if the Hifishield is broken or not, is to install on my C2 a known image that works with stock kernel and Hifishield2. I remember from the past Volumio.
[edit]
I can't find Volumio anymore, I will try ubuntu 20.04 minimal.

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Re: Odroid M1 I2S output

Post by mctom »

I never owned it, but isn't SPDIF a separate audio output, selectable in audio server mixer?
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Re: Odroid M1 I2S output

Post by joerg »

Yes, it is. But I wonder that I have all 4 I2S signals when I play music and silence. When I expect that there is a stream on the SPDIF channel, then I think there must be also a stream on the I2S part. In the devicetree copied from solution from @chewitt it seems that it is mixed together.

Code: Select all

&aiu {
	status = "okay";
	pinctrl-0 = <&spdif_out_ao_6_pins &i2s_am_clk_pins &i2s_out_ao_clk_pins &i2s_out_lr_clk_pins &i2s_out_ch01_ao_pins>;
	pinctrl-names = "default";
};

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Re: Odroid M1 I2S output

Post by joerg »

On C2 ubuntu 20.04 minimal, speaker-test is working with Hifishield2! I see all 4 signals like above and bit pattern on DO0. So my Hifishield is still functional.
Need to find the right setting for mainline kernel on M1.
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Re: Odroid M1 I2S output

Post by joerg »

I have ordered a cheap PCM5102 based board now. Let's see if I can make this working on mainline kernel.
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Re: Odroid M1 I2S output

Post by mctom »

You're serious about this. :)

I searched through devicetree Documentation to see if we're missing anything but after a full hour I got nothing to report. :(
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Re: Odroid M1 I2S output

Post by joerg »

Success! With the PCM5102a board I found a working configuration!
I can't get a configuration for 4-wire I2S. It works with 3-wire I2S but I must let the SCLK pin of PCM5102a stay open.
First I got a driver parse error because I forgot the kernel module: CONFIG_SND_SOC_PCM5102A=m
After several uncountable compiling of the devicetree and reboots, now it works with speaker-test, but also with ffplay. :)
The PCM5102a doesn't have mixer controls, so alsamixer shows nothing.
And without simple-audio-card,bitclock-inversion; I had only sound cracks.

Code: Select all

	pcm5102a: pcm5102a {
		compatible = "ti,pcm5102a";
		#sound-dai-cells = <0>;
		status = "okay";
	};
	
	i2s-sound {
		compatible = "simple-audio-card";
		
		simple-audio-card,name = "I2S_SOC";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,bitclock-master = <&sndcpu>;
		simple-audio-card,frame-master = <&sndcpu>;
		simple-audio-card,bitclock-inversion;

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&i2s1_8ch>;
		};

		sndcodec: simple-audio-card,codec {
			sound-dai = <&pcm5102a>;
			#sound-dai-cells = <0>;
		};
	};
	
&i2s1_8ch {
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1m1_sclktx>, <&i2s1m1_lrcktx>, <&i2s1m1_sdo0>; 
	status = "okay";
};

My Hifishield2 is waste, somehow yesterday it has fried. I never tried to remove and solder a 32 VQFN 0.5 pitch IC. To small for this old guy :(
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Re: Odroid M1 I2S output

Post by mctom »

Splendid news! Thank you for your work and sacrifice :)

In the meantime I investigated M1 schematic to see whether some other SDO pin is also available somewhere, so I could build a 4-channel amp.
There is only one, SDO1 available on DSI connector (as TOUCH_RST).
Extracting this signal is technically doable, but I don't feel like it's worth sacrificing DSI port just for that.

Next stop will be me trying to get TAS5805M to work, based on your configuration.

Is this possible to transform your config into an overlay? I suppose you also removed some entries from the device tree.
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Re: Odroid M1 I2S output

Post by joerg »

mctom wrote:
Fri Jun 14, 2024 2:30 pm
Is this possible to transform your config into an overlay? I suppose you also removed some entries from the device tree.
Yes it is. Yesterday it was late and I have done only some cleaning in my device tree changes. But in the kernel 6.8.x, there are no overlays at all and we must look also, if the here used U-Boot supports it.

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Re: Odroid M1 I2S output

Post by joerg »

I have created an overlay file that compiled without errors. But I can't get it load from u-boot. Sure I am making something wrong.
I have changed /boot/config.ini:

Code: Select all

[generic]
#default_console=ttyFIQ0
overlay_resize=16384
overlay_profile=
overlays="pcm5102a"

[overlay_custom]
overlays="pcm5102a"

[overlay_hktft32]
overlays="hktft32 ads7846"
In /boot/boot.scr, this is already there:

Code: Select all

if test "x{overlays}" != "x"; then
    for overlay in ${overlays}; do
        fdt resize ${overlay_resize}
        load ${devtype} ${devnum}:${partition} ${loadaddr} ${prefix}dtbs/${fk_kvers}/rockchip/overlays/${board}/${overlay}.dtbo \
                && fdt apply ${loadaddr}
    done
fi
My overlay is also there:

Code: Select all

joerg@server:/boot$ ls -la /boot/dtbs/6.8.6-odroid-arm64/rockchip/overlays/odroidm1
total 12
drwxr-xr-x 2 root root 4096 Jun 14 11:28 .
drwxr-xr-x 3 root root 4096 Jun 14 11:27 ..
-rw-r--r-- 1 root root 1492 Jun 14 11:28 pcm5102a.dtbo
And the overlay source is:

Code: Select all

/dts-v1/;
/plugin/;
#include <dt-bindings/soc/rockchip,vop2.h>

/ {
    fragment@0 {
        __overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;
			pcm5102a: pcm5102a {
				compatible = "ti,pcm5102a";
				#sound-dai-cells = <0>;
				status = "okay";
			};
        };
    };

    fragment@1 {
		target = <&i2s1_8ch>;
        __overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2s1m1_sclktx>, <&i2s1m1_lrcktx>, <&i2s1m1_sdo0>;
        };
    };

    fragment@2 {
        __overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;
			i2s-sound {
				compatible = "simple-audio-card";

				simple-audio-card,name = "I2S_SOC";
				simple-audio-card,format = "i2s";
				simple-audio-card,mclk-fs = <256>;
				simple-audio-card,bitclock-master = <&sndcpu>;
				simple-audio-card,frame-master = <&sndcpu>;
				simple-audio-card,bitclock-inversion;

				sndcpu: simple-audio-card,cpu {
					sound-dai = <&i2s1_8ch>;
				};

				sndcodec: simple-audio-card,codec {
					sound-dai = <&pcm5102a>;
					#sound-dai-cells = <0>;
				};
			};
        };
    };
};
@tobetter, do you know what I am making wrong? It's your image ubuntu-server 23.10 for M1 with custom kernel 6.8.y.
I also would like to add some echo messages to boot.scr and then sudo update-bootscript, but I don't know where is the boot.scr template.

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Re: Odroid M1 I2S output

Post by joerg »

Here is some more information.
I have found the template and added some echo... But I can't see them at the serial debug port.
Also I am wondering why debug log says kernel 4.19, but I boot in real into 6.8.6?

Code: Select all

Welcome to Ubuntu 23.10 (GNU/Linux 6.8.6-odroid-arm64 aarch64)
new boot.scr:

Code: Select all

#
# flash-kernel: bootscr.odroid-rk3568
#

# Bootscript using the new unified bootcmd handling
#
# Expects to be called with the following environment variables set:
#
#  devtype              e.g. mmc/scsi etc
#  devnum               The device number of the given type
#  bootpart             The partition containing the boot files
#                       (introduced in u-boot mainline 2016.01)
#  prefix               Prefix within the boot partiion to the boot files
#  kernel_addr_r        Address to load the kernel to
#  fdt_addr_r           Address to load the FDT to
#  ramdisk_addr_r       Address to load the initrd to.
#
# The uboot must support the booti and generic filesystem load commands.

if test -z "${variant}"; then
    setenv variant m1
fi
setenv board odroid${variant}

setenv bootargs " ${bootargs} root=UUID=6b5ededc-4131-4ba3-b19a-7a458a67a4a1 rootwait ro quiet"
setenv overlay_resize 8192

setenv bootlabel "Ubuntu 23.10"

# Default TTY console
setenv bootargs "${bootargs} console=tty1 console=ttyS2,1500000"

# MISC
#
setenv bootargs "${bootargs} pci=nomsi"
setenv bootargs "${bootargs} fsck.mode=force fsck.repair=yes"
setenv bootargs "${bootargs} net.ifnames=0"

load ${devtype} ${devnum}:${partition} ${loadaddr} ${prefix}config.ini \
    &&  ini generic ${loadaddr}
if test -n "${overlay_profile}"; then
    ini overlay_${overlay_profile} ${loadaddr}
fi

if test -n "${console}"; then
  setenv bootargs "${bootargs} console=${console}"
fi

if test -n "${default_console}"; then
  setenv bootargs "${bootargs} console=${default_console}"
fi

if test -z "${fk_kvers}"; then
   setenv fk_kvers "6.8.6-odroid-arm64"
fi

if test -z "${fdtfile}"; then
   setenv fdtfile "rk3568-odroid-${variant}.dtb"
fi

if test -z "${distro_bootpart}"; then
  setenv partition ${bootpart}
else
  setenv partition ${distro_bootpart}
fi



load ${devtype} ${devnum}:${partition} ${fdt_addr_r} ${prefix}dtbs/${fk_kvers}/${fdtfile} \
	|| load ${devtype} ${devnum}:${partition} ${fdt_addr_r} ${prefix}dtbs/${fk_kvers}/rockchip/${fdtfile}
fdt addr ${fdt_addr_r}

echo "Checking overlays for board: ${board} on ${prefix} and kernel version ${fk_kvers}" 
echo "Overlays: {overlays}"

if test "x{overlays}" != "x"; then
    for overlay in ${overlays}; do
        echo "Applying overlay ${overlay}"
        fdt resize ${overlay_resize}
        load ${devtype} ${devnum}:${partition} ${loadaddr} ${prefix}dtbs/${fk_kvers}/rockchip/overlays/${board}/${overlay}.dtbo \
                && fdt apply ${loadaddr}
    done
fi

#load ${devtype} ${devnum}:${partition} ${ramdisk_addr_r} ${prefix}vmlinuz-${fk_kvers} \
#&& unzip ${ramdisk_addr_r} ${kernel_addr_r} \
#&& load ${devtype} ${devnum}:${partition} ${ramdisk_addr_r} ${prefix}initrd.img-${fk_kvers} \
#&& echo "Booting Debian ${fk_kvers} from ${devtype} ${devnum}:${partition}..." \
#&& booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}

load ${devtype} ${devnum}:${partition} ${kernel_addr_r} ${prefix}vmlinuz-${fk_kvers} \
&& load ${devtype} ${devnum}:${partition} ${ramdisk_addr_r} ${prefix}initrd.img-${fk_kvers} \
&& echo "Booting Debian ${fk_kvers} from ${devtype} ${devnum}:${partition}..." \
&& booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}

Code: Select all

/ # DDR Version V1.09 20210630
In
ddrconfig:7
LPDDR4X, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
tdqss: cs0 dqs0: 24ps, dqs1: -96ps, dqs2: -48ps, dqs3: -144ps, 
tdqss: cs1 dqs0: 24ps, dqs1: -96ps, dqs2: -48ps, dqs3: -144ps, 

change to: 324MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:41%
dram drv:40,odt:0
clk skew:0x62

change to: 528MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:41%
dram drv:40,odt:0
clk skew:0x58

change to: 780MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:41%
dram drv:40,odt:0
clk skew:0x58

change to: 1560MHz(final freq)
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:22%
dram drv:40,odt:80
vref_ca:00000071
clk skew:0x21
cs 0:
the read training result:
DQS0:0x34, DQS1:0x37, DQS2:0x38, DQS3:0x31, 
min  :0x10 0x11 0x15 0x10  0x1  0x8  0xb  0x3 , 0xa  0x9  0x2  0x1 0x11  0xa  0xd  0x9 ,
      0x11 0x13  0xc  0xa  0x5  0x1  0x2  0x8 , 0xc  0x8  0x8  0x2 0x11 0x11  0xc  0xe ,
mid  :0x29 0x2b 0x2d 0x2c 0x1c 0x22 0x24 0x20 ,0x26 0x25 0x1e 0x1f 0x2c 0x27 0x27 0x25 ,
      0x2c 0x2d 0x26 0x26 0x21 0x1e 0x1d 0x21 ,0x27 0x23 0x22 0x1f 0x29 0x2b 0x28 0x29 ,
max  :0x43 0x45 0x45 0x48 0x38 0x3c 0x3d 0x3e ,0x43 0x42 0x3b 0x3e 0x47 0x45 0x42 0x42 ,
      0x48 0x48 0x41 0x42 0x3d 0x3b 0x38 0x3a ,0x42 0x3e 0x3d 0x3c 0x42 0x45 0x44 0x45 ,
range:0x33 0x34 0x30 0x38 0x37 0x34 0x32 0x3b ,0x39 0x39 0x39 0x3d 0x36 0x3b 0x35 0x39 ,
      0x37 0x35 0x35 0x38 0x38 0x3a 0x36 0x32 ,0x36 0x36 0x35 0x3a 0x31 0x34 0x38 0x37 ,
the write training result:
DQS0:0x25, DQS1:0xe, DQS2:0x18, DQS3:0x5, 
min  :0x6f 0x73 0x74 0x71 0x62 0x66 0x6a 0x69 0x68 ,0x55 0x50 0x4b 0x4c 0x55 0x52 0x57 0x53 0x4e ,
      0x62 0x63 0x5c 0x5b 0x53 0x52 0x55 0x59 0x59 ,0x4f 0x4d 0x4a 0x48 0x51 0x51 0x4f 0x55 0x4a ,
mid  :0x8b 0x8e 0x8f 0x8c 0x7a 0x7e 0x84 0x82 0x80 ,0x6f 0x6c 0x64 0x66 0x6f 0x6c 0x70 0x6e 0x68 ,
      0x80 0x7f 0x77 0x76 0x6e 0x6c 0x6f 0x73 0x73 ,0x69 0x68 0x64 0x62 0x6a 0x6c 0x69 0x6e 0x64 ,
max  :0xa7 0xa9 0xab 0xa8 0x92 0x96 0x9e 0x9c 0x98 ,0x8a 0x89 0x7e 0x81 0x8a 0x87 0x8a 0x8a 0x83 ,
      0x9e 0x9c 0x92 0x92 0x8a 0x87 0x89 0x8d 0x8e ,0x83 0x83 0x7e 0x7c 0x83 0x88 0x83 0x88 0x7e ,
range:0x38 0x36 0x37 0x37 0x30 0x30 0x34 0x33 0x30 ,0x35 0x39 0x33 0x35 0x35 0x35 0x33 0x37 0x35 ,
      0x3c 0x39 0x36 0x37 0x37 0x35 0x34 0x34 0x35 ,0x34 0x36 0x34 0x34 0x32 0x37 0x34 0x33 0x34 ,
cs 1:
the read training result:
DQS0:0x33, DQS1:0x36, DQS2:0x36, DQS3:0x30, 
min  :0x10 0x10 0x14 0x10  0x2  0x8  0xb  0x3 , 0xb  0x9  0x2  0x1 0x10  0xa  0xe  0x8 ,
      0x11 0x12  0xc  0xb  0x4  0x2  0x2  0x8 , 0xb  0x8  0x8  0x2 0x12 0x10  0xa  0xe ,
mid  :0x29 0x29 0x2c 0x2b 0x1c 0x21 0x23 0x20 ,0x26 0x25 0x1d 0x1e 0x2b 0x26 0x27 0x23 ,
      0x2c 0x2c 0x25 0x26 0x1f 0x1d 0x1d 0x20 ,0x25 0x22 0x22 0x1e 0x28 0x29 0x25 0x28 ,
max  :0x42 0x43 0x45 0x47 0x37 0x3a 0x3c 0x3d ,0x41 0x41 0x39 0x3b 0x46 0x43 0x41 0x3f ,
      0x47 0x47 0x3f 0x42 0x3a 0x38 0x38 0x38 ,0x40 0x3d 0x3c 0x3a 0x3f 0x43 0x41 0x42 ,
range:0x32 0x33 0x31 0x37 0x35 0x32 0x31 0x3a ,0x36 0x38 0x37 0x3a 0x36 0x39 0x33 0x37 ,
      0x36 0x35 0x33 0x37 0x36 0x36 0x36 0x30 ,0x35 0x35 0x34 0x38 0x2d 0x33 0x37 0x34 ,
the write training result:
DQS0:0x25, DQS1:0xe, DQS2:0x18, DQS3:0x5, 
min  :0x6d 0x71 0x71 0x70 0x60 0x64 0x6a 0x67 0x67 ,0x55 0x51 0x4c 0x4e 0x56 0x54 0x59 0x55 0x50 ,
      0x60 0x62 0x59 0x58 0x51 0x50 0x53 0x57 0x57 ,0x4f 0x4e 0x4a 0x48 0x53 0x53 0x4f 0x55 0x47 ,
mid  :0x8a 0x8c 0x8e 0x8b 0x78 0x7e 0x83 0x81 0x7e ,0x6f 0x6d 0x65 0x67 0x70 0x6e 0x71 0x6f 0x6a ,
      0x7e 0x7d 0x74 0x75 0x6c 0x6a 0x6d 0x71 0x72 ,0x6a 0x69 0x65 0x62 0x6a 0x6e 0x6a 0x70 0x63 ,
max  :0xa7 0xa8 0xab 0xa7 0x91 0x99 0x9d 0x9c 0x96 ,0x8a 0x8a 0x7f 0x81 0x8b 0x89 0x8a 0x8a 0x85 ,
      0x9c 0x99 0x90 0x92 0x88 0x84 0x88 0x8c 0x8d ,0x85 0x84 0x80 0x7d 0x82 0x89 0x85 0x8b 0x7f ,
range:0x3a 0x37 0x3a 0x37 0x31 0x35 0x33 0x35 0x2f ,0x35 0x39 0x33 0x33 0x35 0x35 0x31 0x35 0x35 ,
      0x3c 0x37 0x37 0x3a 0x37 0x34 0x35 0x35 0x36 ,0x36 0x36 0x36 0x35 0x2f 0x36 0x36 0x36 0x38 ,
CA Training result:
cs:0 min  :0x53 0x55 0x48 0x48 0x47 0x44 0x4e ,0x4e 0x4c 0x45 0x42 0x44 0x42 0x4d ,
cs:0 mid  :0x93 0x92 0x86 0x85 0x85 0x81 0x80 ,0x8e 0x8b 0x82 0x80 0x83 0x80 0x7e ,
cs:0 max  :0xd3 0xd0 0xc5 0xc2 0xc4 0xbf 0xb2 ,0xce 0xca 0xbf 0xbe 0xc2 0xbe 0xaf ,
cs:0 range:0x80 0x7b 0x7d 0x7a 0x7d 0x7b 0x64 ,0x80 0x7e 0x7a 0x7c 0x7e 0x7c 0x62 ,
cs:1 min  :0x4d 0x59 0x44 0x4c 0x43 0x48 0x51 ,0x4c 0x53 0x42 0x48 0x41 0x46 0x4d ,
cs:1 mid  :0x91 0x91 0x86 0x85 0x85 0x80 0x83 ,0x90 0x8d 0x83 0x81 0x84 0x80 0x80 ,
cs:1 max  :0xd6 0xc9 0xc9 0xbe 0xc8 0xb8 0xb6 ,0xd4 0xc7 0xc5 0xbb 0xc7 0xba 0xb4 ,
cs:1 range:0x89 0x70 0x85 0x72 0x85 0x70 0x65 ,0x88 0x74 0x83 0x73 0x86 0x74 0x67 ,
out
U-Boot SPL board init
U-Boot SPL 2017.09 (Mar 06 2022 - 16:29:16)
Trying to boot from MMC1
MMC error: The cmd index is 0, ret is -110
mmc_init: -110, time 4
spl: mmc init failed with error: -110
Trying to boot from MMC2
MMC error: The cmd index is 1, ret is -110
Card did not respond to voltage select!
mmc_init: -95, time 10
spl: mmc init failed with error: -95
Trying to boot from MTD2
No misc partition
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(0d5225a4ab...) + OK
## Checking uboot 0x00a00000 ... sha256(3be0100dfb...) + OK
## Checking fdt 0x00b369d8 ... sha256(5ef3435c4d...) + OK
## Checking atf-2 0xfdcc1000 ... sha256(3e94d16e6a...) + OK
## Checking atf-3 0x0006b000 ... sha256(fde0ef262b...) + OK
## Checking atf-4 0xfdcce000 ... sha256(c9eb312bf2...) + OK
## Checking atf-5 0xfdcd0000 ... sha256(befba422b8...) + OK
## Checking atf-6 0x00069000 ... sha256(6ede7a3b44...) + OK
## Checking optee 0x08400000 ... sha256(4fcbcd3870...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 234.741 ms

INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-607-gbf602aff1:cl
NOTICE:  BL31: Built : 10:16:03, Jun  5 2023
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    pmu v1 is valid 220114
INFO:    dfs DDR fsp_param[0].freq_mhz= 1560MHz
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
I/TC: 
I/TC: OP-TEE version: 3.13.0-723-gdcfdd61d0 #hisping.lin (gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))) #2 Wed Jun  7 09:43:57 CST 2023 aarch64
I/TC: Primary CPU initializing
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9


U-Boot 2017.09 (Jan 09 2024 - 01:53:35 +0000)

Model: Hardkernel ODROID-M1
MPIDR: 0x81000000
PreSerial: 2, raw, 0xfe660000
DRAM:  7.7 GiB
Sysmem: init
Relocation Offset: ecb2a000
Relocation fdt: eb1f86a8 - eb1fecd0
CR: M/C/I
SF: Detected sfc_nor with page size 256 Bytes, erase size 4 KiB, total 16 MiB
Bootdev(atags): mtd 2
## Unknown partition table type 0
PartType: <NULL>
SF: Detected sfc_nor with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x400000, size 0xc00000
SF: 12582912 bytes @ 0x400000 Read: OK
device 0 offset 0xe0000, size 0x20000
SF: 131072 bytes @ 0xe0000 Read: OK
MMC error: The cmd index is 0, ret is -110
mmc_init: -110, time 49
** Bad device mmc 2 **
MMC error: The cmd index is 0, ret is -110
mmc_init: -110, time 49
** Bad device mmc 2 **
MMC error: The cmd index is 0, ret is -110
mmc_init: -110, time 49
** Bad device mmc 2 **
DM: v1
### CRAMFS load complete: 127256 bytes loaded to 0x8300000
### CRAMFS load complete: 6428 bytes loaded to 0x2000000
Error binding driver 'gpio_led': -22
Some drivers failed to bind
I2c3 speed: 100000Hz
PMIC:  RK8090 (on=0x40, off=0x00)
vdd_logic init 900000 uV
vdd_gpu init 900000 uV
vdd_npu init 900000 uV
io-domain: OK
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
MMC:   dwmmc@fe2b0000: 1, dwmmc@fe2c0000: 2, sdhci@fe310000: 0
Could not find baseparameter partition
Rockchip UBOOT DRM driver version: v1.0.1
VOP have 2 active VP
vp0 have layer nr:3[1 3 5 ], primary plane: 5
vp1 have layer nr:3[0 2 4 ], primary plane: 4
vp2 have layer nr:0[], primary plane: 0
Using display timing dts
dsi@fe060000:  detailed mode clock 132000 kHz, flags[a]
    H: 1080 1095 1097 1127
    V: 1920 1935 1937 1952
bus_format: 100e
VOP update mode to: 1080x1920p60, type: MIPI0 for VP1
VP1 set crtc_clock to 132000KHz
VOP VP1 enable Smart0[1920x1080->1080x1080@0x420] fmt[0] addr[0xed800000]
final DSI-Link bandwidth: 876 Mbps x 4
hdmi@fe0a0000 disconnected
Model: Hardkernel ODROID-M1
MPIDR: 0x81000000
** Bad device mmc 3 **
### CRAMFS load complete: 41831 bytes loaded to 0x2000000
Device 'gpio0@fdd60000': seq 0 is in use by 'gpio@fdd60000'
No misc partition
boot mode: None
VOP VP1 enable Smart0[1280x720->1080x720@0x600] fmt[1] addr[0xedfe907a]
hdmi@fe0a0000 disconnected
CLK: (sync kernel. arm: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
  apll 816000 KHz
  dpll 780000 KHz
  gpll 1188000 KHz
  cpll 1000000 KHz
  npll 1200000 KHz
  vpll 660000 KHz
  hpll 24000 KHz
  ppll 200000 KHz
  armclk 816000 KHz
  aclk_bus 150000 KHz
  pclk_bus 100000 KHz
  aclk_top_high 500000 KHz
  aclk_top_low 400000 KHz
  hclk_top 150000 KHz
  pclk_top 100000 KHz
  aclk_perimid 300000 KHz
  hclk_perimid 150000 KHz
  pclk_pmu 100000 KHz
Invalid bus 0 (err=-19)
Failed to initialize SPI flash at 0:0 (error -19)
No SPI flash selected. Please run `sf probe'
No SPI flash selected. Please run `sf probe'
No SPI flash selected. Please run `sf probe'
Net:   
Error: ethernet@fe2a0000 address not set.
No ethernet found.
Hit key to stop autoboot('CTRL+C'):  0 
### CRAMFS load complete: 1941 bytes loaded to 0xc00000
## Executing script at 00c00000
Card did not respond to voltage select!
mmc_init: -95, time 10
** Bad device mmc 1 **
Card did not respond to voltage select!
mmc_init: -95, time 10
** Bad device mmc 1 **
MMC error: The cmd index is 0, ret is -110
mmc_init: -110, time 49
** Bad device mmc 2 **
### CRAMFS load complete: 4946642 bytes loaded to 0x280000
### CRAMFS load complete: 3256997 bytes loaded to 0xa200000
### CRAMFS load complete: 6428 bytes loaded to 0x2000000
No FDT memory address configured. Default at 0x08300000
Fdt Ramdisk skip relocation
No misc partition
## Booting kernel from Legacy Image at 00280000 ...
   Image Name:   
   Image Type:   AArch64 Linux Kernel Image (gzip compressed)
   Data Size:    4946578 Bytes = 4.7 MiB
   Load Address: 01080000
   Entry Point:  01080000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 0a200000 ...
   Image Name:   
   Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
   Data Size:    3256933 Bytes = 3.1 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 0x08300000
   Booting using the fdt blob at 0x08300000
   Uncompressing GZIP Kernel Image from 0x00280040 to 0x01080000 ... with 00a87008 bytes OK
   kernel loaded at 0x01080000, end = 0x01b07008
   reserving fdt memory region: addr=8300000 size=28000
   Using Device Tree in place at 0000000008300000, end 000000000832afff
vp0, plane_mask:0x2a, primary-id:5, curser-id:-1
vp1, plane_mask:0x15, primary-id:4, curser-id:-1
vp2, plane_mask:0x0, primary-id:0, curser-id:-1
## reserved-memory:
  drm-logo@00000000: addr=edfe9000 size=548000
  ramoops@110000: addr=110000 size=f0000
  pcie3x2@80900000: addr=80900000 size=100000
Adding bank: 0x00200000 - 0x08400000 (size: 0x08200000)
Adding bank: 0x09400000 - 0xf0000000 (size: 0xe6c00000)
Adding bank: 0x100000000 - 0x200000000 (size: 0x100000000)
Total: 2351.359/2393.977 ms

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[    0.000000] Linux version 4.19.206 (odroid@6d97c4fdc17d) (gcc version 6.3.1 20170109 (Linaro GCC 6.3-2017.02), GNU ld
I can't see if it loads the overlay...

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joerg
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Re: Odroid M1 I2S output

Post by joerg »

Now I have figured out, the right dtbo for PCM5102A. I had to update the u-boot on my M1 to mainline, to get this working. On stock u-boot I never saw in the logs that overlays are applied or not.
With this knowledge we can, for sure, make also other sound chips work. :)
pcm5102a.dtso

Code: Select all

/dts-v1/;
/plugin/;
#include <dt-bindings/soc/rockchip,vop2.h>

/ {
    fragment@0 {
		target-path = "/";
        __overlay__ {
			pcm5102a: pcm5102a {
				compatible = "ti,pcm5102a";
				#sound-dai-cells = <0>;
				status = "okay";
			};
        };
    };

    fragment@1 {
		target = <&i2s1_8ch>;
        __overlay__ {
			pinctrl-names = "default";
			pinctrl-0 = <&i2s1m1_sclktx>, <&i2s1m1_lrcktx>, <&i2s1m1_sdo0>;
			status = "okay";
        };
    };

    fragment@2 {
		target-path = "/";
        __overlay__ {
			i2s-sound {
				compatible = "simple-audio-card";

				simple-audio-card,name = "I2S_SOC";
				simple-audio-card,format = "i2s";
				simple-audio-card,mclk-fs = <256>;
				simple-audio-card,bitclock-master = <&sndcpu>;
				simple-audio-card,frame-master = <&sndcpu>;
				simple-audio-card,bitclock-inversion;

				sndcpu: simple-audio-card,cpu {
					sound-dai = <&i2s1_8ch>;
				};

				sndcodec: simple-audio-card,codec {
					sound-dai = <&pcm5102a>;
					#sound-dai-cells = <0>;
				};
			};
        };
    };
};
Additionally, I have black listed snd_soc_rk817 to not get an error in dmesg.
These users thanked the author joerg for the post:
mctom (Fri Jun 21, 2024 12:13 am)

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mctom
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Re: Odroid M1 I2S output

Post by mctom »

You deserve Superthanks for this. :)
Punk ain't no religious cult, punk means thinking for yourself!
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