Is it possible to get second SPI (SPI1) on 40PIN GPIO pin header?

[aleksas]

From digging a bit in this forum i've fond instructions on maniplating pin designations in 40pin header. After decompiling /media/boot/as/meson64_odroidc4.dtb to meson64_odroidc4.dts using command

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dtc -I dtb meson64_odroidc4.dtb -O dts -o meson64_odroidc4.dts

.
Inside apart from entries specifying spi0 there are entries specifying also spi1. The difference being that spi0 has GPIOX pins assigned and spi1 doesn't. Does it mean that spi1 can be accessed via 40pin header if, for instance, unused GPIO pins are assigned to spi1? Or spi1 isnnt meant for 40pin gpio header?

References:

• Re: Is it possible to repurpose the i2c pins as a third uart

• Enable the SPI feature on your board

[tobetter]

No, you cannot since spi1 is SPI_B is in S905X3 datasheet and pins for the channel are GPIOH_4~7. ODROID-C4 exposed GPIOH_6 and GPIOH_7[/b] to GPIO header, GPIOH_4 and GPIOH_5 are tied internally.

[aleksas]

Is there any other way to get second SPI interface? The goal eventually to get second CAN-BUS working on C4.

[tobetter]

Is there any other way to get second SPI interface? The goal eventually to get second CAN-BUS working on C4.

Why don't you use chip select on SPI bus?

[aleksas]

You mean like in this tutorial ?

[tobetter]

You mean like in this tutorial ?

Yes, another Korean user is also trying the same and we can help sometime after holidays (23/Jan).
viewtopic.php?f=218&t=46153

[aleksas]

Great.
By the way the this tutorial would be more helpful with specific example of device tree modifications necessary to add extra spi. There are links pointing to "the spi node" tree lines as a modification hint, but the lines seem to be off. It is likely that code changed since the links were created, IMHO they should point to specific commit lines instead.
In fact when I decompile /boot/amlogic/meson64_odroidc4.dtb or /media/boot/amlogic/meson64_odroidc4.dtb there is no can0 block similar to this one. Am I looking in the wrong file?

[aleksas]

Correct me if I'm wrong these lines add spi0 and by adding following lines below this block. Assuming that GPIOX_4, GPIOX_7 and GPIOX_6 are not in use.

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	can1: can@1 {
		compatible = "microchip,mcp2515";
		reg = <1>;
		spi-max-frequency = <10000000>;
		status = "disabled";
		gpio-irq = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>;
	};

	can2: can@2 {
		compatible = "microchip,mcp2515";
		reg = <2>;
		spi-max-frequency = <10000000>;
		status = "disabled";
		gpio-irq = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
	};

	can3: can@3 {
		compatible = "microchip,mcp2515";
		reg = <3>;
		spi-max-frequency = <10000000>;
		status = "disabled";
		gpio-irq = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	};

would add extra three can interfaces? Should canX: can@X and reg = <X>; be incremented?

[aleksas]

Also wanted to note that in meson64_odroidc4.dts decompiled from /media/boot/amlogic/meson64_odroidc4.dtb doesn't contain can0 bloc as seen in source meson64_odroidc4.dts file.

[steve.jeong]

The board is "odroid-m1", but it won't make much difference. Please refer to the following link.

viewtopic.php?p=364577#p364577