[SOLVED] C4 stopped booting, uboot log incl.

[gkkpch]

My Odroid C4 has stopped booting, it won't work, whatever image, SD or eMMC is used.
This is the uboot log, it goes into a boot loop after "Stop here"

Code: Select all

SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:00000703
L2:00008067
L3:15000020
B2:20282000
B1:a0f83180

TE: 133577

BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13

Board ID = 1
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
SYS1 pll lock check retry
try t0...
SYS1 pll lock check retry
try t1...
SYS1 pll lock check retry
Stop here...

Anyone any idea?

[igorpec]

On reboot, power cycle or both?

[odroid]

The SoC or DRAM seems to be damaged by uncertain electrical shock.
Which power supply and USB peripherals did you use with C4?
Have run only Debian based Volumio OS?

[gkkpch]

I used the standard HK PSU for the C4, no peripherals.
This was suddenly while testing a new Volumio release, at one point, after applying power, it just failed.
The C4 is used for Volumio only.

[odroid]

Your serial console log looks weird. Seems to have a very old boot blobs or from a N2 platform.
My C4 shows the following messages.

Code: Select all

SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
                                                                                                     
bl2_stage_init 0x01                                                                                  
bl2_stage_init 0x81                                                                                  
hw id: 0x0000 - pwm id 0x01                                                                          
bl2_stage_init 0xc1                                                                                  
bl2_stage_init 0x02                                                                                  
                                                                                                     
L0:00000000                                                                                          
L1:00000703                                                                                          
L2:00008067                                                                                          
L3:15000020                                                                                          
S1:00000000                                                                                          
B2:20282000                                                                                          
B1:a0f83180                                                                                          
                                                                                                     
TE: 308943                                                                                           
                                                                                                     
BL2 Built : 22:54:32, Apr 28 2020. g12a ga659aac-dirty - changqing.gao@droid11                       
                                                                                                     
Board ID = 4                                                                                         
Set cpu clk to 24M                                                                                   
Set clk81 to 24M                                                                                     
Use GP1_pll as DSU clk.                                                                              
DSU clk: 1200 Mhz                                                                                    
CPU clk: 1200 MHz                                                                                    
Set clk81 to 166.6M                                                                                  
eMMC boot @ 0                                                                                        
sw8 s                                                                                                
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Apr 28 2020 22:54:28                              
board id: 4                                                                                          
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
00000000
emmc switch 2 ok
fastboot data verify
verify result: 255
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
00000000
emmc switch 0 ok
                                                                                                     
dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization   

Can you try this Ubuntu image to find anything different?
https://wiki.odroid.com/odroid-c4/os_im ... e/20201214

[gkkpch]

Thanks Odroid! I took and older image and tried that succesfully, somehow my uboot binary must be garbled.
So, it is not the C4 and I should have been able to find that myself, oops