I guess somehow the updating is failed. If updating procedure is correct, you should have this logs and you must be able to see the progress in HDMI display.
Code: Select all
G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.4
bl2_stage_ini1
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
B2:00002000
B1:e0f83180
TE: 371840
BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz
Board ID = 3
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0005f511
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
board id: 3
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
R0_RxClkDly_Margin==94 ps 8
R0_TxDqDly_Margi==106 ps 9
R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00600024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass
pre test bdlr_100_average==461 bdlr_100_min==461 bdlr_100_max==461 bdlr_100_cur==461
aft test bdlr_100_average==461 bdlr_100_min==461 bdlr_100_max==461 bdlr_100_cur==461
100bdlr_step_size ps== 467
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0003c200, des: 0x0172c000, size: 0x00098000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
E30HDR
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz]
OPS=0x40
ring efuse init
chipver efuse init
29 0a 40 00 01 03 17 00 00 19 34 37 57 4e 4b 50
[0.019924 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):ab8811b
NOTICE: BL31: Built : 15:03:31, Feb 12 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Apr 08 2019 - 03:40:07)
DRAM: 3.5 GiB
Relocation Offset is: d6ef5000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7f86728
MMC: aml_priv->desc_buf = 0x00000000d3ee57c0
aml_priv->desc_buf = 0x00000000d3ee7b00
SDIO Port C: 0, SDIO Port B: 1
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x12000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
In: serial
Out: serial
Err: serial
vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
vpu: clk_level = 7
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_clk_gate_init_off finish
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs_config_hdmipll_g12a
cvbs_set_vid2_clk
reading boot-logo.bmp.gz
** Unable to read file boot-logo.bmp.gz **
reading boot-logo.bmp
** Unable to read file boot-logo.bmp **
movi: not registered partition name, logo
movi - Read/write command from/to SD/MMC for ODROID board
Usage:
movi <read|write> <partition|sector> <offset> <address> [<length>]
- <read|write> the command to access the storage
- <offset> the offset from the start of given partiton in lba
- <address> the memory address to load/store from/to the storage device
- [<length>] the size of the block to read/write in bytes
- all parameters must be hexa-decimal only
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]set initrd_high: 0x3d800000
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3d800000 width=5760, height=2160
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 1.4 or below div=10
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
## Executing script at 01000000
Wrong image format for "source" command
reading boot.ini
995 bytes read in 4 ms (242.2 KiB/s)
## Executing script at 01000000
reading uImage
3615093 bytes read in 203 ms (17 MiB/s)
reading rootfs.cpio.uboot
2904681 bytes read in 164 ms (16.9 MiB/s)
reading meson64_odroidn2_spibios.dtb
68307 bytes read in 10 ms (6.5 MiB/s)
ee_gate_off ...
## Booting kernel from Legacy Image at 04000000 ...
Image Name:
Image Type: AArch64 Linux Kernel Image (gzip compressed)
Data Size: 3615029 Bytes = 3.4 MiB
Load Address: 01080000
Entry Point: 01080000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 03080000 ...
Image Name:
Image Type: AArch64 Linux RAMDisk Image (uncompressed)
Data Size: 2904617 Bytes = 2.8 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
load dtb from 0x1000000 ......
## Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
Uncompressing Kernel Image ... OK
kernel loaded at 0x01080000, end = 0x01903808
reserving fdt memory region: addr=1000000 size=11000
Loading Ramdisk to 3d53a000, end 3d7ff229 ... OK
Loading Device Tree to 000000001ffec000, end 000000001fffffff ... OK
Starting kernel ...
uboot time: 7694995 us