best_odroidfreak wrote:MCLK (I2S MCLK on J7) used by the C2/C1+ is generated by the 24MHz clock and PLL dividers. Odroid C2 need drivers for i2s to configure the clocks and dividers for best audio output.
I might be a little wrong with some of the technical details but this is my understanding to date.
Firstly in regards to I2S output
I2S Clock pins on the 7 pin header
Pin 4 - GPIOAO.8 (I2S_AM_CLK) Master clock out is set to output (and is output only) at a rate that will be comparable / compatable with the DAC. Its not necessarily required but desirable for best audio quality. This clock is closest to the 24Mhz Crystal
Pin 5 - GPIOAO.10 (I2S_LR_CLK) Either configured as in or out (out by default) Left / Right Clock. Otherwise known as the word clock and will be synced at ratio to master clock (if no master clock output to the DAC the DAC must have another source which is matched to master clock as close as possible)
Pin 6 - GPIOAO.9 (I2S_AO_CLK) Either configured as in or out (out by default and same as LR_CLK) Data Clock. Otherwise known as the bit clock and will be synced at ratio to master and word clock
Master clock is controlled by divisors from the 24Mhz Crystal which is controlled by registers in the S905 and the word clock and bit clocks can be selected by registers to divide which will match the data format. The drivers do support some modification to the clock here but the data formats need to be matched. The master clock for I2S is output only (no input) so might be better to use internal clock for all divisors rather than an external clock for word and bit clocks although it should be possible to get very close.
Data format for I2S is by default (same as the older meson8 chip) 1 pin with 2 channels (Right Justified but could be easily modified to Left Justified) and 24bit words carrying 16 bit audio I believe with the left over zeroed out (a standard type of transmission) This pin is I2SOUT_CH01 or pin 7 on the 7 pin header. There is another accessible pin on the 40 pin header (or 3 on S905 but 2 have no out pins on the C2 headers), pin 31 named I2SOUT_CH23 which is not accessible by the drivers. If the drivers supported It could possibly support another 2 channels of audio on the other pin in Right Justified mode without changing any of the clocks.
The S905 gxbb also has additional parallel encoding streams to read the bits from DDR which is not currently supported in the drivers. This can theoretically increase the bit-rate meaning higher output rates or more channels (would be required to effectively use the 2nd I2S pin above) or could even be used to multiplex up to 8 channels into the 1 pin in TDM (Time division Multiplex) mode (ie up to 8 channels output on a single I2S data pin). The drivers do not support this either. Some others in LibeELEC have outputted 8 channels in bypass mode for HDMI but this is not using the I2S encoding function of the C2 and simply bypassing it with a prebuilt stream from a properly encoded video / audio stream.
For changes to the output encoding the clocks must be modified from the defaults.
Input from what I can tell is not really supported although I do believe some have it working in default single channel mode.
Additionally drivers do not support mmap functionality to read directly from the DDR allocated to the Audio FIFOs and do not make use of the most efficient real-time encoding in the hardware.
SPDIF output pins and PCM pins for audio is also an option and can make use of the parallel encoders in the S905 which are currently not being used due to drivers, and the same goes with the PCM output pins. There is also an input PCM avaliable along with an input PCM pin. I am not sure of the number of channels that can be obtained on the PCM but I suspect 8 is possible along with TDM mode.