C2 - External I2S Master Clocks possible?

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C2 - External I2S Master Clocks possible?

Unread postby jrling » Sat Feb 11, 2017 7:38 am

I understand the MCLK (I2S MCLK on J7) used by the C1+ is generated by the 24MHz clock and PLL dividers.
I want to explore some other options that, potentially, can achieve lower phase noise/lower jitter to feed my DAC.

The idea is to use an external board between the C2 and the DAC to provide galvanic isolation and "high quality" reclocking before the DAC. With that in mind:

Can one disable the internal 24Mhz clock and provide my own clocks to the board.
In this case, the external board provide 2 high quality clocks (45.1584/49.152MHz dual master clocks) to drive the C2 and the reclocker in sync mode.


In 2015 a member asked this question about C1+.
Can it now be done with C2?

Thanks
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Re: C2 - External I2S Master Clocks possible?

Unread postby brad » Mon Feb 13, 2017 8:39 pm

jrling wrote:
I understand the MCLK (I2S MCLK on J7) used by the C1+ is generated by the 24MHz clock and PLL dividers.
I want to explore some other options that, potentially, can achieve lower phase noise/lower jitter to feed my DAC.

The idea is to use an external board between the C2 and the DAC to provide galvanic isolation and "high quality" reclocking before the DAC. With that in mind:

Can one disable the internal 24Mhz clock and provide my own clocks to the board.
In this case, the external board provide 2 high quality clocks (45.1584/49.152MHz dual master clocks) to drive the C2 and the reclocker in sync mode.


In 2015 a member asked this question about C1+.
Can it now be done with C2?

Thanks


I think the hardware can but the software/ OS in its current state cannot. Im attempting to look at providing drivers for I2S, PCM and SPDIF inputs/outputs and are struggling with the internal odroid clocks and dividers at the moment.

The ALSA driver software in the kernel provides a dedicated I2S clock output with currently no option to change, but if the drivers can be modified (im trying to work on it) then there is a possibility of selecting an external I2S_AO_CLK_IN and I2S_LR_CLK_IN
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Re: C2 - External I2S Master Clocks possible?

Unread postby crashoverride » Mon Feb 20, 2017 9:35 am

The datasheet (p.205) shows a clock selection register:
AIU_clk_ctrl 0x16

(Bit 10)
clock source selection
0 => aiclk from pin
1 => ai_pll_clk from pll
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Re: C2 - External I2S Master Clocks possible?

Unread postby brad » Mon Feb 20, 2017 10:12 pm

crashoverride wrote:The datasheet (p.205) shows a clock selection register:
AIU_clk_ctrl 0x16

(Bit 10)
clock source selection
0 => aiclk from pin
1 => ai_pll_clk from pll


I seen this as well with my head in the code, but I think there is a little more to be done including synchronizing audio FIFOs and PCM clocks for the incoming I2S clock sources
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Re: C2 - External I2S Master Clocks possible?

Unread postby best_odroidfreak » Fri May 12, 2017 4:45 am

brad wrote:
jrling wrote:
I understand the MCLK (I2S MCLK on J7) used by the C1+ is generated by the 24MHz clock and PLL dividers.
I want to explore some other options that, potentially, can achieve lower phase noise/lower jitter to feed my DAC.

The idea is to use an external board between the C2 and the DAC to provide galvanic isolation and "high quality" reclocking before the DAC. With that in mind:

Can one disable the internal 24Mhz clock and provide my own clocks to the board.
In this case, the external board provide 2 high quality clocks (45.1584/49.152MHz dual master clocks) to drive the C2 and the reclocker in sync mode.


In 2015 a member asked this question about C1+.
Can it now be done with C2?

Thanks


I think the hardware can but the software/ OS in its current state cannot. Im attempting to look at providing drivers for I2S, PCM and SPDIF inputs/outputs and are struggling with the internal odroid clocks and dividers at the moment.

The ALSA driver software in the kernel provides a dedicated I2S clock output with currently no option to change, but if the drivers can be modified (im trying to work on it) then there is a possibility of selecting an external I2S_AO_CLK_IN and I2S_LR_CLK_IN

Hi Brad and thank you for your work!
Please explain what difficulties do you have with the internal odroid clocks and dividers at the moment?
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Re: C2 - External I2S Master Clocks possible?

Unread postby brad » Fri May 12, 2017 10:34 am

The drivers do not support the options to configure the clocks, dividers and other hardware registers but instead rely on the default boot configuration. In addition they are based upon meson8 and miss aditional features of the gxbb hardware including additional clocks, internal dacs and multiplexing functions
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Re: C2 - External I2S Master Clocks possible?

Unread postby best_odroidfreak » Fri May 12, 2017 7:41 pm

brad wrote:The drivers do not support the options to configure the clocks, dividers and other hardware registers but instead rely on the default boot configuration. In addition they are based upon meson8 and miss aditional features of the gxbb hardware including additional clocks, internal dacs and multiplexing functions

MCLK (I2S MCLK on J7) used by the C2/C1+ is generated by the 24MHz clock and PLL dividers. Odroid C2 need drivers for i2s to configure the clocks and dividers for best audio output.
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Re: C2 - External I2S Master Clocks possible?

Unread postby brad » Fri May 12, 2017 10:07 pm

best_odroidfreak wrote:MCLK (I2S MCLK on J7) used by the C2/C1+ is generated by the 24MHz clock and PLL dividers. Odroid C2 need drivers for i2s to configure the clocks and dividers for best audio output.


I might be a little wrong with some of the technical details but this is my understanding to date.

Firstly in regards to I2S output

I2S Clock pins on the 7 pin header
Pin 4 - GPIOAO.8 (I2S_AM_CLK) Master clock out is set to output (and is output only) at a rate that will be comparable / compatable with the DAC. Its not necessarily required but desirable for best audio quality. This clock is closest to the 24Mhz Crystal
Pin 5 - GPIOAO.10 (I2S_LR_CLK) Either configured as in or out (out by default) Left / Right Clock. Otherwise known as the word clock and will be synced at ratio to master clock (if no master clock output to the DAC the DAC must have another source which is matched to master clock as close as possible)
Pin 6 - GPIOAO.9 (I2S_AO_CLK) Either configured as in or out (out by default and same as LR_CLK) Data Clock. Otherwise known as the bit clock and will be synced at ratio to master and word clock

Master clock is controlled by divisors from the 24Mhz Crystal which is controlled by registers in the S905 and the word clock and bit clocks can be selected by registers to divide which will match the data format. The drivers do support some modification to the clock here but the data formats need to be matched. The master clock for I2S is output only (no input) so might be better to use internal clock for all divisors rather than an external clock for word and bit clocks although it should be possible to get very close.

Data format for I2S is by default (same as the older meson8 chip) 1 pin with 2 channels (Right Justified but could be easily modified to Left Justified) and 24bit words carrying 16 bit audio I believe with the left over zeroed out (a standard type of transmission) This pin is I2SOUT_CH01 or pin 7 on the 7 pin header. There is another accessible pin on the 40 pin header (or 3 on S905 but 2 have no out pins on the C2 headers), pin 31 named I2SOUT_CH23 which is not accessible by the drivers. If the drivers supported It could possibly support another 2 channels of audio on the other pin in Right Justified mode without changing any of the clocks.

The S905 gxbb also has additional parallel encoding streams to read the bits from DDR which is not currently supported in the drivers. This can theoretically increase the bit-rate meaning higher output rates or more channels (would be required to effectively use the 2nd I2S pin above) or could even be used to multiplex up to 8 channels into the 1 pin in TDM (Time division Multiplex) mode (ie up to 8 channels output on a single I2S data pin). The drivers do not support this either. Some others in LibeELEC have outputted 8 channels in bypass mode for HDMI but this is not using the I2S encoding function of the C2 and simply bypassing it with a prebuilt stream from a properly encoded video / audio stream.

For changes to the output encoding the clocks must be modified from the defaults.

Input from what I can tell is not really supported although I do believe some have it working in default single channel mode.

Additionally drivers do not support mmap functionality to read directly from the DDR allocated to the Audio FIFOs and do not make use of the most efficient real-time encoding in the hardware.

SPDIF output pins and PCM pins for audio is also an option and can make use of the parallel encoders in the S905 which are currently not being used due to drivers, and the same goes with the PCM output pins. There is also an input PCM avaliable along with an input PCM pin. I am not sure of the number of channels that can be obtained on the PCM but I suspect 8 is possible along with TDM mode.
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Re: C2 - External I2S Master Clocks possible?

Unread postby best_odroidfreak » Sat May 13, 2017 2:16 am

Thank you for providing us valuable information!
1) As I understand Odroid c2 board allows access to the I2S pins? Isn't it?
2) One more question, help you anybody from Hardkernel to write new I2S driver for Odroid c2?
3) See tread about single board computers with I2s http://www.diyaudio.com/forums/pc-based ... sound.html



brad wrote:
best_odroidfreak wrote:MCLK (I2S MCLK on J7) used by the C2/C1+ is generated by the 24MHz clock and PLL dividers. Odroid C2 need drivers for i2s to configure the clocks and dividers for best audio output.


I might be a little wrong with some of the technical details but this is my understanding to date.

Firstly in regards to I2S output

I2S Clock pins on the 7 pin header
Pin 4 - GPIOAO.8 (I2S_AM_CLK) Master clock out is set to output (and is output only) at a rate that will be comparable / compatable with the DAC. Its not necessarily required but desirable for best audio quality. This clock is closest to the 24Mhz Crystal
Pin 5 - GPIOAO.10 (I2S_LR_CLK) Either configured as in or out (out by default) Left / Right Clock. Otherwise known as the word clock and will be synced at ratio to master clock (if no master clock output to the DAC the DAC must have another source which is matched to master clock as close as possible)
Pin 6 - GPIOAO.9 (I2S_AO_CLK) Either configured as in or out (out by default and same as LR_CLK) Data Clock. Otherwise known as the bit clock and will be synced at ratio to master and word clock

Master clock is controlled by divisors from the 24Mhz Crystal which is controlled by registers in the S905 and the word clock and bit clocks can be selected by registers to divide which will match the data format. The drivers do support some modification to the clock here but the data formats need to be matched. The master clock for I2S is output only (no input) so might be better to use internal clock for all divisors rather than an external clock for word and bit clocks although it should be possible to get very close.

Data format for I2S is by default (same as the older meson8 chip) 1 pin with 2 channels (Right Justified but could be easily modified to Left Justified) and 24bit words carrying 16 bit audio I believe with the left over zeroed out (a standard type of transmission) This pin is I2SOUT_CH01 or pin 7 on the 7 pin header. There is another accessible pin on the 40 pin header (or 3 on S905 but 2 have no out pins on the C2 headers), pin 31 named I2SOUT_CH23 which is not accessible by the drivers. If the drivers supported It could possibly support another 2 channels of audio on the other pin in Right Justified mode without changing any of the clocks.

The S905 gxbb also has additional parallel encoding streams to read the bits from DDR which is not currently supported in the drivers. This can theoretically increase the bit-rate meaning higher output rates or more channels (would be required to effectively use the 2nd I2S pin above) or could even be used to multiplex up to 8 channels into the 1 pin in TDM (Time division Multiplex) mode (ie up to 8 channels output on a single I2S data pin). The drivers do not support this either. Some others in LibeELEC have outputted 8 channels in bypass mode for HDMI but this is not using the I2S encoding function of the C2 and simply bypassing it with a prebuilt stream from a properly encoded video / audio stream.

For changes to the output encoding the clocks must be modified from the defaults.

Input from what I can tell is not really supported although I do believe some have it working in default single channel mode.

Additionally drivers do not support mmap functionality to read directly from the DDR allocated to the Audio FIFOs and do not make use of the most efficient real-time encoding in the hardware.

SPDIF output pins and PCM pins for audio is also an option and can make use of the parallel encoders in the S905 which are currently not being used due to drivers, and the same goes with the PCM output pins. There is also an input PCM avaliable along with an input PCM pin. I am not sure of the number of channels that can be obtained on the PCM but I suspect 8 is possible along with TDM mode.
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Re: C2 - External I2S Master Clocks possible?

Unread postby brad » Sat May 13, 2017 9:55 am

best_odroidfreak wrote:Thank you for providing us valuable information!
1) As I understand Odroid c2 board allows access to the I2S pins? Isn't it?

Odroid allows access to some of the pins but not all

7Pin
=====
Pin 2 - GPIOAO.6 (I2S_IN_01) I2S input data channel 0+1 (this pin can alternatively be set for SPDIF out)
Pin 4 - GPIOAO.8 (I2S_AM_CLK) Master clock out
Pin 5 - GPIOAO.10 (I2S_LR_CLK) Can either configured as in or out (out by default) Left / Right Clock.
Pin 6 - GPIOAO.9 (I2S_AO_CLK) Either configured as in or out (out by default and same as LR_CLK) Data Clock.
Pin 7 - GPIOAO.11 (I2SOUT_CH01) - output data channel 0+1

40Pin
=====
Pin 31 - GPIOY.8 (I2SOUT_CH23) - output data channel 2+3
Pin 35 - GPIOY.3 (I2SIN_CH67) - Input data channel 6+7

So all up 2 out of 4 channels input and 2 out of 4 channels output avaliable on the Odroid. Another channel almost available but connected to the blue status led

best_odroidfreak wrote:2) One more question, help you anybody from Hardkernel to write new I2S driver for Odroid c2?


I have not written any of the drivers, I did try to enhance the the amlogic / hardkernel ones but did not progress to far, my main downfall was the very old alsa version they were based on.

Jerome Brunet and BayLibre is working on gxbb alsa drivers for 4.12 kernel but its a WIP

https://github.com/jeromebrunet/linux/c ... /wip/audio

best_odroidfreak wrote:3) See tread about single board computers with I2s http://www.diyaudio.com/forums/pc-based ... sound.html


I will read through that post, you can check out this document from TI which describes clock synchronisation for audio and the different configuration for master clock http://www.ti.com/lit/an/slaa469/slaa469.pdf
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Re: C2 - External I2S Master Clocks possible?

Unread postby best_odroidfreak » Sun May 14, 2017 12:16 am

brad wrote:
best_odroidfreak wrote:Thank you for providing us valuable information!
1) As I understand Odroid c2 board allows access to the I2S pins? Isn't it?

Odroid allows access to some of the pins but not all

7Pin
=====
Pin 2 - GPIOAO.6 (I2S_IN_01) I2S input data channel 0+1 (this pin can alternatively be set for SPDIF out)
Pin 4 - GPIOAO.8 (I2S_AM_CLK) Master clock out
Pin 5 - GPIOAO.10 (I2S_LR_CLK) Can either configured as in or out (out by default) Left / Right Clock.
Pin 6 - GPIOAO.9 (I2S_AO_CLK) Either configured as in or out (out by default and same as LR_CLK) Data Clock.
Pin 7 - GPIOAO.11 (I2SOUT_CH01) - output data channel 0+1

40Pin
=====
Pin 31 - GPIOY.8 (I2SOUT_CH23) - output data channel 2+3
Pin 35 - GPIOY.3 (I2SIN_CH67) - Input data channel 6+7

So all up 2 out of 4 channels input and 2 out of 4 channels output avaliable on the Odroid. Another channel almost available but connected to the blue status led

best_odroidfreak wrote:2) One more question, help you anybody from Hardkernel to write new I2S driver for Odroid c2?


I have not written any of the drivers, I did try to enhance the the amlogic / hardkernel ones but did not progress to far, my main downfall was the very old alsa version they were based on.

Jerome Brunet and BayLibre is working on gxbb alsa drivers for 4.12 kernel but its a WIP

https://github.com/jeromebrunet/linux/c ... /wip/audio

best_odroidfreak wrote:3) See tread about single board computers with I2s http://www.diyaudio.com/forums/pc-based ... sound.html


I will read through that post, you can check out this document from TI which describes clock synchronisation for audio and the different configuration for master clock http://www.ti.com/lit/an/slaa469/slaa469.pdf

Thank you !
See Clock Slave Mode With Master/System Clock (SCK) Input for pcm510xA http://www.ti.com/lit/ds/symlink/pcm5102a.pdf
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Re: C2 - External I2S Master Clocks possible?

Unread postby alexruedi » Wed Aug 22, 2018 4:43 am

Any update on this?

I try to use jack and hifi shield but using dummy driver and alsa_out (as mmap is not supported) causes clock drifts or anything. It works for up to 40 seconds before the issues begin.
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