Exploring CPU clock speeds on the C2

[mlinuxguy]

default clocks
Prior to rebuilding the kernel and checking overclock limits I thought it would be useful to see how the default kernel clocks are setup

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root@odroid64:/sys/devices/system/cpu/cpufreq# cat all_time_in_state
freq            cpu0            cpu1            cpu2            cpu3
100000          0               0               0               0
250000          0               0               0               0
500000          0               0               0               0
1000000         0               0               0               0
1296000         0               0               0               0
1536000         0               0               0               0
1752000         0               0               0               0
2016000         815556          815556          815556          815556

So it appears to be spending all its time at max freq if I'm reading that right

Let's check what the governor is

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root@odroid64:/sys/devices/system/cpu# cd cpu0/cpufreq/
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat cpuinfo_cur_freq
2016000
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat cpuinfo_max_freq
2016000
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat cpuinfo_min_freq
100000
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat scaling_available_frequencies
100000 250000 500000 1000000 1296000 1536000 1752000 2016000
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat scaling_available_governors
hotplug performance
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat scaling_governor
performance

So its setup for performance currently and running at max freq

Lets set it up to hotplug for the governor
root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# echo hotplug > scaling_governor

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root@odroid64:/sys/devices/system/cpu/cpu0/cpufreq# cat /sys/devices/system/cpu/cpufreq/all_time_in_state
freq            cpu0            cpu1            cpu2            cpu3
100000          0               0               0               0
250000          1906            1906            1906            1906
500000          10              10              10              10
1000000         10              10              10              10
1296000         0               0               0               0
1536000         0               0               0               0
1752000         0               0               0               0
2016000         848828          848828          848828          848828

As we would expect we now spend time down in lower CPU frequencies

Next up, figure out how to overclock and find the C2 limits

[rooted]

I'm not sure if it's worth the effort but I'm curious as well.

Never know, may be able to squeeze another 200mhz out of it.

[mlinuxguy]

Searching for the correct place to overclock
First up was to check the output of dmesg to see what cpufreq driver was active
I found this in the dmesg output

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[    0.028986] /cpus/cpu@0: Missing clock-frequency property
[    0.029015] /cpus/cpu@1: Missing clock-frequency property
[    0.029028] /cpus/cpu@2: Missing clock-frequency property
[    0.029040] /cpus/cpu@3: Missing clock-frequency property

Not sure what that means yet...

From the .config file for the C2

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# CONFIG_AMLOGIC_MESON_CPUFREQ is not set
CONFIG_AMLOGIC_SCPI_CPUFREQ=y

The easiest method to add overclocks would have been to edit: cpufreq_table.h
but that is used by meson-cpufreq.c which we aren't using.

Instead we are using: cpufreq-scpi.c
Which is a bit more complicated to extend.

[mlinuxguy]

The dmesg error output:
[ 0.029040] /cpus/cpu@3: Missing clock-frequency property

Comes from this file: /usr/src/linux/arch/arm64/kernel/topology.c
In the routine:
264 static void __init parse_dt_cpu_power(void)

Where it tries to find the clock-frequency

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296         rate = of_get_property(cn, "clock-frequency", &len);
297         if (!rate || len != 4) {
298             pr_err("%s: Missing clock-frequency property\n",
299                 cn->full_name);
300             continue;
301         }

So it appears the call is made to determine CPU topology and frequencies (which fails for frequency)

They do hunt for min_state in the DTS file
In file:

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148     if (of_property_read_u32_array(np, "min_state", min_buf, 4)) {
149         dev_err(&pdev->dev, "read min_state failed\n");
150         min_exist = 0;
151     } else {
152         dev_info(&pdev->dev, "min state:%d %d %d %d\n",
153              min_buf[0], min_buf[1], min_buf[2], min_buf[3]);
154         min_exist = 1;
155     }

Which is specified in the DTS file:

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    aml_sensor0: aml-sensor@0 {
        compatible = "amlogic, aml-thermal";
        #thermal-sensor-cells = <1>;
        cpu_dyn_coeff = <140>;
        /* cpu_freq gpu_freq cpu_core gpu_core */
        min_state = <1000000 400 1 2>;
        gpu_dyn_coeff = <437>;
    };

We could need frequency values set in the device tree... more investigation needed

An example of how clock-frequency might be used is in DTS file: fvp-base-gicv2-psci.dts

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    cpus {
        #address-cells = <2>;
        #size-cells = <0>;

        big0: cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a57", "arm,armv8";
            reg = <0x0 0x0>;
            enable-method = "psci";
            clock-frequency = <1000000>;
        };
        big1: cpu@1 {
            device_type = "cpu";
            compatible = "arm,cortex-a57", "arm,armv8";
            reg = <0x0 0x1>;
            enable-method = "psci";
            clock-frequency = <1000000>;
        };

amlogic does include the file: amlogic/mesongxbb.dtsi
Which gets close but no frequency per cpu specified

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    cpus:cpus {
        #address-cells = <2>;
        #size-cells = <0>;
        #cooling-cells = <2>; /* min followed by max */

        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a53","arm,armv8";
            reg = <0x0 0x0>;
            enable-method = "psci";
            timer=<&timer_f>;
        };

[mlinuxguy]

Apparently they are using OPP for the clock/voltage table
ref: https://www.kernel.org/doc/Documentation/power/opp.txt

from file: /usr/src/linux/include/linux/amlogic/scpi_protocol.h

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struct scpi_opp_entry {
    u32 freq_hz;
    u32 volt_mv;
} __packed;

And in file: /usr/src/linux/drivers/amlogic/mailbox/scpi_protocol.c
is the code to read the table

[mlinuxguy]

Going to give up on the overclock for now
It appears the scpi commands are part of the ARM64 -- Application Processor (AP) Trusted Firmware

I might try using the meson driver later and see if it works.

[mlinuxguy]

I am running with a 2.2ghz clock right now (Overclock)
I did a little hack to add 2 additional frequencies to the top-end

OC: 2,112,000,000
OC: 2,208,000,000

Current temps at idle are 42F, I will run some benchmarks and see how stable this is

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# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
2208000

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# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
100000 250000 500000 1000000 1296000 1536000 1752000 2016000 2112000 2208000

Here is the hack, I would like to figure out a way to eventually add a cleaner approach to adding overclock frequencies... perhaps via device-tree optional entries

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root@odroid64:/usr/src/linux/drivers/amlogic/cpufreq# diff cpufreq-scpi.c.orig cpufreq-scpi.c
206c206,207
<       meson_freq_table = kzalloc(sizeof(*meson_freq_table) * (max_opp + 1),
---
>       /* was max_opp + 1,  for OC change to:  max_opp + 3 for 2 OC values */
>       meson_freq_table = kzalloc(sizeof(*meson_freq_table) * (max_opp + 3),
212,213c213,214
<                       ret = dev_pm_opp_add(cpu_dev, opp->freq_hz,
<                                            opp->volt_mv*1000);
---
>                       pr_info("\tIndex=%d,freq=%d\n",idx,meson_freq_table[idx].frequency);
>                       ret = dev_pm_opp_add(cpu_dev, opp->freq_hz, opp->volt_mv*1000);
219a221,244
>       /* OC: add 2 extra overclock values */
>       opp--;  /* re-use last entry for OC variable and mvolts */
>       meson_freq_table[idx].driver_data = idx;
>       opp->freq_hz = 2112000000;
>       meson_freq_table[idx].frequency = opp->freq_hz/1000;
>       pr_info("\tIndex=%d,freq=%d\n",idx,meson_freq_table[idx].frequency);
>       ret = dev_pm_opp_add(cpu_dev, opp->freq_hz, opp->volt_mv*1000);
>       if (ret) {
>               pr_warn("failed to add OC #1 opp %uHz %umV\n",
>               opp->freq_hz, opp->volt_mv);
>               return ret;
>       }
>       idx++;  /* increment for 2nd OC freq */
>       meson_freq_table[idx].driver_data = idx;
>       opp->freq_hz = 2208000000;
>       meson_freq_table[idx].frequency = opp->freq_hz/1000;
>       pr_info("\tIndex=%d,freq=%d\n",idx,meson_freq_table[idx].frequency);
>       ret = dev_pm_opp_add(cpu_dev, opp->freq_hz, opp->volt_mv*1000);
>       if (ret) {
>               pr_warn("failed to add OC #2 opp %uHz %umV\n",
>               opp->freq_hz, opp->volt_mv);
>               return ret;
>       }
>       idx++;  /* final increment to be freq table end */

I will update this with benchmarks and temperatures later
NOTE: I am re-using the last cpu voltage value for its original max frequency, potentially one could increase that voltage

[mlinuxguy]

Not sure I'm really getting an overclock
I'll need to dig into the code deeper to see where the actual CPU frequency transitions are set
I thought it was reading the frequency / volt settings and then driving them from that table.
However it looks like I just fed numbers to the cpu scaling governor and it doesn't really set the
freq/volt pair to the CPU.

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Normal clock
time echo "scale=5000; a(1)*4" | bc -l
real    1m11.968s
user    1m11.920s
sys     0m0.000s

Overclock 2.2ghz
time echo "scale=5000; a(1)*4" | bc -l
real    1m11.872s
user    1m11.840s
sys     0m0.000s

[mlinuxguy]

Results of much research on overclocking the C2
- I have changed the code where the dvfs_opps table has overclocked values that CPUFREQ uses, however the M3 co-processor does not
appear to use those values and ignores settings I add via the call:

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 dev_pm_opp_add(cpu_dev, opp->freq_hz, opp->volt_mv*1000);

- I have changed the C2 defconfg to use: meson-cpufreq.c (and fixed the code so it would compile)
However even though it uses some calls that should adjust voltages and frequency it also fails to change to
OC'd frequencies, and will disable the kernel's ability to use CPU governors.
- I looked into the u-boot C2 code and can see where it does register writes to set the boot frequency
however it never writes a table of freq-voltages to the M3 (which apparently uses factory set values)
Instead it computes a nominal frequency and gets on with doing u-boot stuff...

The next option is the S905 technical PDF
Once this is released we should be able to program the CPU frequency and voltages directly.
I'm still unclear on what effect directly programming a CPU clock frequency has when
there appears to be an un-reachable set of freq/volt values the chip itself will attempt to use.
Perhaps a deeper study of the thermal limit code will show what triggers the CPU to drop frequencies..

Optional extra: Turbo-Boost mode
This occurred to me after running across the boost mode frequency support in the C2's kernel.
We could add a turbo boost frequency and temperature, if the temperature max is hit it will drop
out of turbo mode into its normal frequency set.
To do this we would still need the S905 tech manual to create code to overclock the CPU's
We could set the Turbo frequency, voltage, and max temperature in the device-tree, if its
not there, then there is no turbo mode.

Technical clock trivia on the C2
These are the fixed clocks. XTAL at 24mhz is base frequency, clock freqs are multiples of this

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[    0.136065] == Registering fixed clocks
[    0.136080] === clock name: xtal, parent name: (null), rate: 24000000
[    0.136094] === clock name: 32Khz, parent name: (null), rate: 32000
[    0.136106] === clock name: clk81, parent name: (null), rate: 166666666
[    0.136118] === clock name: fixed_pll, parent name: (null), rate: 2000000000
[    0.136130] === clock name: fclk_div2, parent name: (null), rate: 1000000000
[    0.136143] === clock name: fclk_div3, parent name: (null), rate: 666666000
[    0.136155] === clock name: fclk_div4, parent name: (null), rate: 500000000
[    0.136167] === clock name: fclk_div5, parent name: (null), rate: 400000000
[    0.136179] === clock name: fclk_div7, parent name: (null), rate: 285714000

This is the overclock table I built and used scpi to set

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[    4.187696] == scpi_dvfs_get_opps: scpi_opps[domain] already populated
[    4.194134] == Adding meson_freq_table
[    4.197872] ==       Index=0,freq=100000
[    4.201208] == opp_add_dynamic: freq=100000000
[    4.205620] ==               freq=100000000, volt=860
[    4.209494] ==       Index=1,freq=250000
[    4.212850] == opp_add_dynamic: freq=250000000
[    4.217270] ==               freq=250000000, volt=860
[    4.221130] ==       Index=2,freq=500000
[    4.224493] == opp_add_dynamic: freq=500000000
[    4.228900] ==               freq=500000000, volt=860
[    4.232787] ==       Index=3,freq=1000000
[    4.236224] == opp_add_dynamic: freq=1000000000
[    4.240716] ==               freq=1000000000, volt=940
[    4.244676] ==       Index=4,freq=1296000
[    4.248161] == opp_add_dynamic: freq=1296000000
[    4.252604] ==               freq=1296000000, volt=980
[    4.256600] ==       Index=5,freq=1536000
[    4.260021] == opp_add_dynamic: freq=1536000000
[    4.264506] ==               freq=1536000000, volt=1050
[    4.268567] ==       Index=6,freq=1752000
[    4.272010] == opp_add_dynamic: freq=1752000000
[    4.276501] ==               freq=1752000000, volt=1050
[    4.280548] ==       Index=7,freq=2016000
[    4.283998] == opp_add_dynamic: freq=2112000000
[    4.288490] ==               freq=2112000000, volt=1100
[    4.292542] == meson_cpufreq_init: pmin=100000,pmax=2112000,cpuinfo_min=100000, cpuinfo_max=2112000

An example of one of the PLL clocks and its multiplier being set

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[    0.136407] == aml_pll2500_recalc_rate: prate=24000000, fvco=1536000000, od=0, M=64, N=1, ext_div_n=5

Note: It appears it would be relatively easy to overclock the GPU...