PCM interface on 40pin header

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PCM interface on 40pin header

Unread postby brad » Sun May 14, 2017 11:55 am

Hi Hardkernel,
I have been analysing the potential PCM interface in the S905 and the interface on the 40pin header and from the datasheet I am struggling to understand exactly what the hardware can support.

Firstly the pins on the header

- Pin12 - PCM_FS_A - PCM frame synchronisation
- Pin13 - PCM_CLK_A - PCM master clock input
- Pin15 - PCM_IN_A - PCM input stream
- Pin16 - PCM_OUT_A - PCM output stream

So it seems PCM operates in slave mode and I can supply an external high frequency PCM clock and Frame Sync input to the interface but I can not determine minimum and maximum timings from the datasheet. In addition I cannot determine how many channels may be supported by the interface and any limitations on the sample rate. Is it possible for hardkernel / amlogic to provide any further information for me to look at? I am suspecting 8 in and 8 out will be supported as per the internal PCM encoder/ decoder.

Next the I2S interface and pins on the 7 pin header can support PCM TDM mode. in this case I am assuming that I am limited to using the I2S master clock (I2S_AM_CLK) as a control PLL for the external PCM device and then use the bit clock pin (I2S_AO_CLK) as the PCM output clock and the left right clock pin (I2S_LR_CLK) as the frame sync clock. Then I can use the DOUT and DIN as 8 channel PCM interfaces.

The datasheet specifies that PCM and I2S (7.1) Modes can be supported at the same time so potentially if my assumptions are right this ends up supporting 16 channel input and 16 channel output at the same time using both PCM and I2S interfaces. PCM in slave mode and I2S in master mode.

Im currently trying to produce an external board for some evaluation and testing of the interfaces and any further information from amlogic would be greatly appreciated. Would it be more appropriate to ask these questions directly to amlogic or via hardkernel?

Any assistance would be appreciated.

Thanks,
Brad.
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Re: PCM interface on 40pin header

Unread postby odroid » Sun May 14, 2017 1:42 pm

Let's try to calculate the maximum bit clock.
192Khz * 24bit * Stereo could be 9.216Mhz if there is no over-sampling.
If you consider simultaneous 8 channels, It could be over 36.864Mhz.

When we tested 384Khz * 32bit * Stereo with our HiFi Shield, the maximum bit clock was 24.576Mhz and it worked well on the I2S master mode.
But I have no idea about the PCM slave mode either TDM mode. I've never seen that,
Do you have any specific audio DAC/ADC chipset to implement multi-channel sound system?

Because Amlogic never tried the PCM interface, I don't think they will give us proper answers.
But let me ask them. Please make a list of questions with more information.
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Re: PCM interface on 40pin header

Unread postby brad » Sun May 14, 2017 9:04 pm

Thank you odroid, I will make a list of question and let you know tomorrow.

The codec's I am looking into at the moment are

Texas Instruments PCM3169A
Analog Devices AD1937 or similar (Can dasiy chain these
Cirrus Logic CS42438, CS42448 or CS42888 (might only be possible with slave clock on the I2s)

Im only really aiming for max 96KHz (even 48KHz) but would like to over-sample so this will bring up the clock rate. Ill work out the ideal formats and correlate. Im thinking 36.864Mhz will be max with 96KHz double sampled as this is generally the limitation of the ADC's on these chips. DAC could probably push 192KHz double sampled (or quad sampled) with 73.728MHz clock but this would be an overkill and not work with the ADC. Page 55 of the S905 datasheet shows the Audio PLL frequency chart so I was hoping what I could input a similar range which would be comparable on the PCM. I2C drivers exist for each of these chips for the software control interface.
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Re: PCM interface on 40pin header

Unread postby odroid » Mon May 15, 2017 9:54 am

When we measured the MCLK output, it could be up to near 50Mhz.
384Khz * 128fs = 49.152Mhz.

BTW, I couldn't find PCM3169A in TI homepage.
http://www.ti.com/lsds/ti/audio-ic/audi ... oduct.page
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Re: PCM interface on 40pin header

Unread postby brad » Mon May 15, 2017 10:49 am

odroid wrote:When we measured the MCLK output, it could be up to near 50Mhz.
384Khz * 128fs = 49.152Mhz.

BTW, I couldn't find PCM3169A in TI homepage.
http://www.ti.com/lsds/ti/audio-ic/audi ... oduct.page


Sorry thats a typo should be the pcm3168a. From your testing it seem clocks will meet my needs. Will post some questions regarding pcm interface later when i make some calculations. Thanks
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Re: PCM interface on 40pin header

Unread postby brad » Tue May 16, 2017 5:16 pm

Here are my questions

1) HHI_PCM_CLK_CNTL - is there further information regarding this register? datasheet says "See the Clock Tree document for information related to cts_pcm_sclk" & also pcm_mclk
2) There are 2 internal PCM controls controlled by PCMIN_CTRL1 & PCMIN1_CTRL1 bit 28 of each register selects the clock ( 1= internal from cts_pcm_clk. 0 = external PCM interface). Can 1 control with cts_pcm_clk and the other with external PCM clock?
3) For PCMIN_CTRL1 & PCMIN1_CTRL1 bits 15:0 provide enable for up to 16 slots on each control can I use them all?
4) SImilar questions for PCMOUT_CTRL0 and PCMOUT1_CTRL0 PCM output controls, can I use both at the same time one with external PCM clock input and other with I2S output clock?
5) What is the maximum input clock for PCM_CLK_A pin?
6) What is the maximum output clock for I2S_AM_CLK when the interface is placed into PCM TDM mode?
7) What is the maximum channels for each interface (PCM & I2S) when running at the same time? (8 channel in and out on each using PCM TDM mode for I2S)
8) Are there any restrictions on running different clock rates on each of the PCM controls at the same time?
9) Can I use the I2S_AM_CLK (I2S master clock) as an output clock for the PCM pin interface and ignore the PCM_CLK_A input pin (ie use the PCM pin interface as a slave?)
10) Can I output to HDMI at the same time with the same 8 channel data used for the I2S interface (or even PCM interface)?

I understand some if this may be unknown and I am prepared to test but any known limitations would be most helpful in the design stage.

49.152Mhz would be the max clock rates I would be looking for.

Any information appreciated,

Thanks,
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Re: PCM interface on 40pin header

Unread postby odroid » Tue May 16, 2017 6:37 pm

I will try to understand your questions before forwarding. I need 1~2 days to compile your questions.

BTW, do you think the PCM3168A can be connected the 4 PCM pins in the first post?
Any other missing signals?
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Re: PCM interface on 40pin header

Unread postby brad » Tue May 16, 2017 7:05 pm

odroid wrote:I will try to understand your questions before forwarding. I need 1~2 days to compile your questions.

BTW, do you think the PCM3168A can be connected the 4 PCM pins in the first post?
Any other missing signals?


That is fine, im working on schematics and pcb board design at the moment which will take some more time.

I think that the PCM3168A can be connected to the PCM interface.

On page 34 of the TI datasheet Figure 52. Audio Data Format: 24-Bit TDM Format (SCKI = 128 fS, 256 fS, and 512 fS Only)

Odroid PCM to TI PCM3168A
- Pin12 - PCM_FS_A connected to LRCKAD/DA (On the S905 PCMIN_CTRL0 register we can set the skew of the left/ right clock to be compatible I believe)
- Pin13 - PCM_CLK_A connected to BCKAD/DA
- Pin15 - PCM_IN_A - connected to DOUT1
- Pin16 - PCM_OUT_A - connected to DIN1

This chip has max 48Khz in this mode

Or high speed mode is slave and DAC only for PCM3168 so might be more suited to the I2S in PCM mode where I know C2 can act as master. Unless of course I can use odroid PCM interface as master (was one of my questions) See page 35 of the TI datasheet for this example Figure 53. Audio Data Format: 24-Bit High-Speed TDM Format (SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only)
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Re: PCM interface on 40pin header

Unread postby brad » Tue May 16, 2017 7:45 pm

Basic schematic for connecting digital PCM interface (Odroid being slave)
BasicPCM.png
Basic connection to PCM interface
BasicPCM.png (137.79 KiB) Viewed 1475 times


Basic setting using I2S PCM (Odroid master) - Added extra DIN & DOUT's for extra compatability with with PCM or I2S modes
BasicI2S.png
Basic I2S
BasicI2S.png (143.66 KiB) Viewed 1474 times
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Re: PCM interface on 40pin header

Unread postby brad » Tue May 16, 2017 8:24 pm

I should have 1 more question for amlgoc, the tolerance of the pins I might need to lower the voltage for the digital pins to not burn out the C2. 1.8v and conversion for the digital signals might be required or maybe it will be happy with 3.3 v digital signals
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Re: PCM interface on 40pin header

Unread postby odroid » Wed May 17, 2017 9:39 pm

All GPIOs on S905 are 3.3Volt and there is no tolerance against 1.8V nor 5V.
What is the digital PCM interface voltage of the PCM3168A?
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Re: PCM interface on 40pin header

Unread postby brad » Wed May 17, 2017 10:05 pm

odroid wrote:All GPIOs on S905 are 3.3Volt and there is no tolerance against 1.8V nor 5V.
What is the digital PCM interface voltage of the PCM3168A?


I see that the Odroid XU4 board has 1,8v I2S (or at least I read some here say on another forum) so was wondering.

The PCM3168A has 3.3v nominal digital interface :)
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Re: PCM interface on 40pin header

Unread postby odroid » Thu May 18, 2017 9:21 am

Bad news.
I had a chance to have a chat with Amlogic people last night.
He told me they can't support us because they never validated the PCM block due to lack of customers.
Sorry about that. :(
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Re: PCM interface on 40pin header

Unread postby brad » Thu May 18, 2017 9:35 am

odroid wrote:Bad news.
I had a chance to have a chat with Amlogic people last night.
He told me they can't support us because they never validated the PCM block due to lack of customers.
Sorry about that. :(


OK, how about PCM mode on the I2S?

Does by not validated mean it wont work/ has not been tested / or just they wont support any problems or provide any information?
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Re: PCM interface on 40pin header

Unread postby odroid » Thu May 18, 2017 3:39 pm

All the OTT Android boxes based on Amlogic SoC have been using a very cheap(~$0.5) I2S stereo DAC.
So Amlogic engineers didn't need to check the PCM output functionality.
If we ask some questions to Amlogic, their engineers need to look into the silicon design drawings to check the interconnection between the PCM registers and pin pads due to poor documentation.
It should take quite long time. They also need a real hardware to check the functionality.
It means they won't support us because there is no information to provide.

I think they should remove the PCM related information from the datasheet if they couldn't support.
The datasheet seemed to be made to catch some big players like Google TV team, Alibaba OTT division and so on. :(
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Re: PCM interface on 40pin header

Unread postby brad » Thu May 18, 2017 4:39 pm

odroid wrote:All the OTT Android boxes based on Amlogic SoC have been using a very cheap(~$0.5) I2S stereo DAC.
So Amlogic engineers didn't need to check the PCM output functionality.
If we ask some questions to Amlogic, their engineers need to look into the silicon design drawings to check the interconnection between the PCM registers and pin pads due to poor documentation.
It should take quite long time. They also need a real hardware to check the functionality.
It means they won't support us because there is no information to provide.

I think they should remove the PCM related information from the datasheet if they couldn't support.
The datasheet seemed to be made to catch some big players like Google TV team, Alibaba OTT division and so on. :(


Thanks for your efforts odroid, its quiet disappointing that amlogic have included specifications in their datasheet that they have not confirmed /tested on the silicon including PCM and 2GHz cpu frequency :(

This does save me some painful trials and testing so thank you.
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Re: PCM interface on 40pin header

Unread postby brad » Wed May 24, 2017 10:32 pm

I might try a few options for some testing, wish me some luck I will start with the I2S interface and try to push PCM output. I have a 4 channel oscilloscope which should hopefully be up to spec for the tests and an audio interface which I have just ordered a breakout cable to input / output clocks. A little work on a basic driver for 4.12 and I should hopefully be able to output some bits :) If that goes well then I will try to produce an interface board.
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Re: PCM interface on 40pin header

Unread postby odroid » Wed May 24, 2017 10:42 pm

Very reasonable approach.
Once you can capture the signal shapes, please share it.
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Re: PCM interface on 40pin header

Unread postby brad » Mon May 29, 2017 5:12 pm

Unfortunately my current scope does not have enough resolution for my testings, I cannot see the master clock. I need to get hold of a better one but this scope allows me to compare the 3 other channels to some degree, PCM_OUT, I2S_AO_CLK and the word clock.

I can however see bitclock, wordclock and some low resolution of the data output. It also shows the bit-clock not synchronised with the data or word clock which can potentially cause issues. Lastly Its in a sign wave format which might not be ideal for I2S or PCM.

Its difficult to see the changing sync in the static image but is jumps all over the place. The accuracy is not good enough to see for definite any jitter in the sync between the word and data out but it looks ok from what I can tell only the bit clock (I2S_AO_CLK) is off.
i2s.jpg
i2s output
i2s.jpg (325.74 KiB) Viewed 1093 times

1st = bit clock
2nd = data out
3rd word or frame sync clock

Next step is to compare against mainline which I am working on getting the output now.
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Re: PCM interface on 40pin header

Unread postby brad » Sat Jun 03, 2017 3:28 pm

brad wrote:Next step is to compare against mainline which I am working on getting the output now.


I patched linux-next with jbrunet's development audio patches, modified a little and have I2S output for es7134 codec (what was used in meson-gxbb-p20x)

The bitclock moves around here too and similar results to original test.
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