Odroid C2 mainline kernel support

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chewitt
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Re: Odroid C2 mainline kernel support

Post by chewitt »

SD cards operate at multiple voltages depending on the speed/mode the card is in. The problem is normally that the card is not reset from sdr50 into the standard mode needed for initial boot during shutdown; hence warm (re)boot fails while cold boot succeeds.

This u-boot patch might help? https://github.com/chewitt/u-boot/commi ... c0cc94c862 .. but I'll have to retest.

tobbe-the-sweede
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Re: Odroid C2 mainline kernel support

Post by tobbe-the-sweede »

Hello!

My Humble 1st post on the forum and I really hope I'm not kicking in to many open doors.
20+ years in networking but just got more into poking around on the OS-side of things (really just started).

I been struggling with suddenly bricked emmc/sd cards on the c2's I have and manage to get serial connectivity to one that died on me.
What I noticed then (and multiple times after that) is that all 2 or 3 symlinks get overwritten during the upgrade (before the reboot) and pointes to older or nonexisting/noncompatible files.
And creating a C2-brick after next reboot.

Manually sorting up the symlinks and then a reboot got me going.

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dietpi@DietPi:/$ find . -maxdepth 1 -type l -ls
      231      0 lrwxrwxrwx   1 root     root            7 Nov 15  2021 ./bin -> usr/bin
     2359      0 lrwxrwxrwx   1 root     root           31 May  3 00:12 ./initrd.img.old -> boot/initrd.img-5.10.0-22-arm64
      498      0 lrwxrwxrwx   1 root     root           31 Jan 29 19:20 ./initrd.img.oold -> boot/initrd.img-5.10.0-21-arm64 <------ saved brick
     2113      0 lrwxrwxrwx   1 root     root           28 May  3 00:12 ./vmlinuz.old -> boot/vmlinuz-5.10.0-22-arm64
      235      0 lrwxrwxrwx   1 root     root            7 Nov 15  2021 ./lib -> usr/lib
     2127      0 lrwxrwxrwx   1 root     root           28 Jan 29 19:20 ./vmlinuz.oold -> boot/vmlinuz-5.10.0-21-arm64  <------ saved brick
      233      0 lrwxrwxrwx   1 root     root            8 Nov 15  2021 ./sbin -> usr/sbin
    25670      0 lrwxrwxrwx   1 root     root           27 May  3 00:01 ./vmlinuz -> boot/vmlinuz-6.1.11-meson64
    25707      0 lrwxrwxrwx   1 root     root           30 May  3 00:01 ./initrd.img -> boot/initrd.img-6.1.11-meson64
dietpi@DietPi:/$ cd boot/
dietpi@DietPi:/boot$ find . -maxdepth 1 -type l -ls
     7503      0 lrwxrwxrwx   1 root     root           18 Apr 22 22:21 ./dtb -> dtb-6.1.11-meson64
      347      0 lrwxrwxrwx   1 root     root           22 Apr 22 22:21 ./Image -> vmlinuz-6.1.11-meson64
     1745      0 lrwxrwxrwx   1 root     root           22 May  3 19:58 ./uInitrd -> uInitrd-6.1.11-meson64
dietpi@DietPi:/boot$

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dietpi@DietPi:/boot$ uname -a
Linux DietPi 6.1.11-meson64 #23.02.2 SMP PREEMPT Sat Feb 18 00:07:55 UTC 2023 aarch64 GNU/Linux
dietpi@DietPi:/boot$

The old C2's is still usable!
These users thanked the author tobbe-the-sweede for the post:
odroid (Thu May 04, 2023 9:03 am)

chewitt
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Re: Odroid C2 mainline kernel support

Post by chewitt »

I had some requests to support the HiFi-Shield mezzanine boards for C2 in LibreELEC and some experimenting has resulted in this:

https://github.com/chewitt/linux/commit ... 7d97ee9f7c
https://github.com/chewitt/linux/commit ... 706ceab466

The kernel needs to have "CONFIG_SND_SOC_PCM5102A=m" (HiFi-Shield v1 and HiFi-Shield +) or "CONFIG_SND_SOC_PCM512x_I2C=m" (HiFi-Shield v2) enabled.

This is a LibreELEC test image that can be written to SD card or eMMC module: http://chewitt.libreelec.tv/testing/Lib ... -c2.img.gz .. After booting the image run "mount -o remount,rw /flash" and copy either /usr/share/bootloader/meson-gxbb-odroidc2-hifishield.dtb or meson-gxbb-odroidc2-hifishield2.dtb to /flash then update the boot config in /flash/extlinux/extlinux.conf with the revised dtb filename to boot.

To experiment with a HiFi-Shield v1 board on some other distro download: http://chewitt.libreelec.tv/testing/Lib ... box.img.gz and steal the relevant dtb file from the "amlogic" folder in the root of the SD card. I'd expect anything from Linux 6.1.y upwards will work. The v2 board dtb will not work as the pcm512x kernel module in your kernel will not be patched with the ti,pcm5242 compatible used in the v2 device-tree.

I've had success reports from users with third-party HAT boards that use the same DAC chip as HiFi-Shield v1, and the v2 board someone posted to me for test/dev shows up and looks like it's working, but I don't have access to anything with S/PDIF and RCA inputs so feedback from users with real boards would be nice :)

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Re: Odroid C2 mainline kernel support

Post by moon.linux »

Can you enable this with Device Tree Overlays, It will be a better option rather than duplicating the DTS changes.

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Re: Odroid C2 mainline kernel support

Post by chewitt »

The long-term goal would be to send some overlays upstream (as upstream accepts them) but first I want to see some success reports.

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Re: Odroid C2 mainline kernel support

Post by moon.linux »

Enable DVFS frequency cpu clock freqency on Odroid C2 boards.
For this, we need to update the u-boot with the latest BL31 image with support

Build the BLI3 image and update the

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$ git clone  https://github.com/ARM-software/arm-trusted-firmware.git
$ cd arm-trusted-firmware
$ CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31
$ cp ./build/gxbb/debug/bl31.bin ../amlogic-boot-fip/odroid-c2/
Build u-boot with new BL31 image

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$ git clone https://source.denx.de/u-boot/u-boot.git
$ cd u-boot
$ export CROSS_COMPILE=aarch64-linux-gnu- 
$ make odroid-c2_defconfig
$ make

# This will build u-boot.bin

$ git clone https://github.com/LibreELEC/amlogic-boot-fip.git
$ cd amlogic-boot-fip
$ 
$ mkdir -p my-output-dir
.$ /build-fip.sh odroid-c2 ../u-boot/u-boot.bin my-output-dir
To flash the image to sdcard or emmc module.

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if [ -b "$FILEB" ]; then
        echo "eMMC module flashing........."
        sudo dd if=my-output-dir/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1
else
        echo "microSD module flashing........."
        sudo dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
        sudo dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
fi
u-boot boot logs with new BL31 image which support

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-- UART initialized after reboot ---
[Reset cause: unknown]
[Image: unknown, amlogic_v1.1.3046-00db6Load bl33 from SD, src: 0x0002c200, des: 0x01000000, size: 0x000bbc30
30-dirty 2016-08-31 09:24:14 tao.zeng@droid04]
bl30: check_permit, count is 1
bl30: check_permit: ok!
chipid: ef be ad de d f0 ad ba ef be ad de not ES chip
[0.474446 Inits done]
secure task start!
high task start!
low task start!
NOTICE:  BL31: v2.11.0(debug):v2.10.0-1015-gaff731af1
NOTICE:  BL31: Built : 20:10:09, Jun  3 2024
INFO:    ARM GICv2 driver initialized
INFO:    BL31: Initializing runtime services
INFO:    BL31: cortex_a53: CPU workaround for erratum 843419 was applied
INFO:    BL31: cortex_a53: CPU workaround for erratum 855873 was applied
WARNING: BL31: cortex_a53: CPU workaround for erratum 1530924 was missing!
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x1000000
INFO:    SPSR = 0x3c9

<debug_uart>


U-Boot 2024.07-rc3-00013-g46ff00bea5d (Jun 03 2024 - 22:33:21 +0530) odroid-c2

Model: Hardkernel ODROID-C2
SoC:   Amlogic Meson GXBB (S905) Revision 1f:c (0:1)
DRAM:  2 GiB
Core:  172 devices, 29 uclasses, devicetree: separate
MMC:   mmc@72000: 0, mmc@74000: 1
Loading Environment from nowhere... OK
In:    usbkbd,serial
Out:   vidconsole,serial
Err:   vidconsole,serial
Net:   eth0: ethernet@c9410000

Hit any key to stop autoboot:  0
Enable dvfs with dts changes

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$ git diff arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index c431986e6a33..4061cfcb3019 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -331,10 +331,6 @@ &saradc {
        vref-supply = <&vcc1v8>;
 };

-&scpi_clocks {
-       status = "disabled";
-};

 /* SD */
 &sd_emmc_b {
        status = "okay";
 
-

Cpufreeq on odroid c2 stable

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alarm@alarm:~$ cpupower frequency-info
analyzing CPU 2:
  driver: scpi-cpufreq
  CPUs which run at the same hardware frequency: 0 1 2 3
  CPUs which need to have their frequency coordinated by software: 0 1 2 3
  maximum transition latency: 200 us
  hardware limits: 100.0 MHz - 1.54 GHz
  available frequency steps:  100.0 MHz, 250 MHz, 500 MHz, 1000 MHz, 1.30 GHz, 1.54 GHz
  available cpufreq governors: conservative ondemand userspace powersave performance schedutil
  current policy: frequency should be within 100.0 MHz and 1.54 GHz.
                  The governor "performance" may decide which speed to use
                  within this range.
  current CPU frequency: Unable to call hardware
  current CPU frequency: 1.54 GHz (asserted by call to kernel)
alarm@alarm:~$
Attach it the build script to build and flash u-boot.
Attachments
c2.ubuild.sh
u-boot build script.
(1.05 KiB) Downloaded 3 times

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MichaIng
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Re: Odroid C2 mainline kernel support

Post by MichaIng »

chewitt wrote:
Fri Mar 03, 2023 7:18 pm
SD cards operate at multiple voltages depending on the speed/mode the card is in. The problem is normally that the card is not reset from sdr50 into the standard mode needed for initial boot during shutdown; hence warm (re)boot fails while cold boot succeeds.

This u-boot patch might help? https://github.com/chewitt/u-boot/commi ... c0cc94c862 .. but I'll have to retest.
We found the following solution for hanging reboot with mainline kernel: https://github.com/MichaIng/DietPi/issu ... 1462629461
But I do not fully understand the reason/issue. In old Linux 3.14/3.16 sources from Hardkernel, the same GPIO is set to active low. However, multiple users verified it working.

The same has been found to solve the same issue on Odroid C4 earlier, which has been upstreamed already: https://github.com/MichaIng/DietPi/issu ... 1266685259
https://git.kernel.org/pub/scm/linux/ke ... d.dtsi#n31

chewitt
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Re: Odroid C2 mainline kernel support

Post by chewitt »

I was able to replicate problems with SD cards locally and the following two changes solved it for me:

https://github.com/chewitt/linux/commit ... a7c0ed570f
https://github.com/chewitt/linux/commit ... b47173eefe

However that didn't work for the user who originally reported issues in the LE forum. He's gone off to acquire a UART cable so we can hopefully see what the problem is.

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Re: Odroid C2 mainline kernel support

Post by moon.linux »

I feel we do not handle all the cases of UHS, we should support TIMING_UHS

Code: Select all

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index c7c067b9415a..39563029270f 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -567,6 +567,10 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host,
        switch (ios->timing) {
        case MMC_TIMING_MMC_DDR52:
        case MMC_TIMING_UHS_DDR50:
+       case MMC_TIMING_UHS_SDR12:
+       case MMC_TIMING_UHS_SDR25:
+       case MMC_TIMING_UHS_SDR50:
+       case MMC_TIMING_UHS_SDR104:
                ddr = true;
                break;


chewitt
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Re: Odroid C2 mainline kernel support

Post by chewitt »

That function is setting "ddr = true" which is presumably why it only includes the DDR modes, not the SDR ones.

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Re: Odroid C2 mainline kernel support

Post by moon.linux »

we are just not handling these tuning nodes the code is common for eMMC and sdcard .
as per the datasheet, it says

You are correct DDR=true is for emmc and ddr=fasle is for sdcard

S905 Datasheet Revision 1.1.4 (Please check the section for SD Mode: table

Code: Select all

The HS200 mode offers the following features:
 SDR Data sampling method
 CLK frequency up to 200MHz Data rate – up to 200MB/s
 4 or 8-bits bus width supported
 Single ended signaling with 4 Drive Strengths
 Signaling levels of 1.8V and 1.2V
 Tuning concept for Read Operations

The HS400 mode has the following features
 DDR Data sampling method
 CLK frequency up to 200MHz, Data rate is up to 400MB/s
 Only 8-bit bus width supported
 Signaling levels of 1.8V and 1.2V
 Support up to 5 Drive Strengths
 Data strobe signal is toggled only for Data out and CRC response

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